L
lssharma.iitd@gmail.com
Guest
I am trying to simulate vhdl code in simulink with the help of
Modelsim, that is made possible by using cosimulation block.
- I have invoked modelsim from matlab using command
vsim('socketsimulink', 4449),
And then i used vsimulink command to simulate that vhdl code. Iam
sending a sampled
signal the cosimulation block. When i started to run the simulation
from simulaink, i am finding the following error.
"Explicit Simulink clocks require a minimum model step time of at
least 2".
The another problem (this is different from above) iam finding is
iam unable to run the simulation continuously if iam
giving external clock to cosimulation block.
Modelsim, that is made possible by using cosimulation block.
- I have invoked modelsim from matlab using command
vsim('socketsimulink', 4449),
And then i used vsimulink command to simulate that vhdl code. Iam
sending a sampled
signal the cosimulation block. When i started to run the simulation
from simulaink, i am finding the following error.
"Explicit Simulink clocks require a minimum model step time of at
least 2".
The another problem (this is different from above) iam finding is
iam unable to run the simulation continuously if iam
giving external clock to cosimulation block.