Problem in linking designs in PrimeTime

[tinoosh]

Hi,

I am using PrimeTime. The input file is a hierarchical netlist. I got
warnings regarding that the software can not find the reference model
in the top file.
It seems that I need to define another link_path to refer to these
modules. However, link_path only accepts .db files(is it right??).
However, these modules are verilog files in one of our design folders
(pipe folder that I defined in search_path).
So I'm not sure how I can link the top file (proc) to these modules.

I appreciate if somebody can give me a any idea how to fix this
problem.

Best Regards,
Tinoosh

**********************************
Here is piece of my script code:
***********************************

set search_path {. /../datapath/pipe } # This is for design files
set link_path {/../typical.db} # This is for library Mosis
files

read_verilog proc08.vg

link_design -keep_sub_designs proc


**************************
Here is the log file:
**************************

source script.pt
Loading verilog file '/../tinoosh/proc08.vg'
Loading db file
'/net/pizza/2/lib/mosis/artisan/sage-x/aci/sc/synopsys/typical.db'
Linking design proc...
Warning: Unable to resolve reference to 'mac' in 'proc'. (LNK-005)
Warning: Unable to resolve reference to 'alu' in 'proc'. (LNK-005)
Warning: Unable to resolve reference to 'repeat_cntr' in 'proc'.
(LNK-005)
Warning: Unable to resolve reference to 'dcmem' in 'proc'. (LNK-005)
Warning: Unable to resolve reference to 'dmem' in 'proc'. (LNK-005)
Warning: Unable to resolve reference to 'FIFO_top_0' in 'proc'.
(LNK-005)
Warning: Unable to resolve reference to 'FIFO_top_1' in 'proc'.
(LNK-005)
Warning: Unable to resolve reference to 'mem_port' in 'proc'. (LNK-005)
Warning: Unable to resolve reference to 'data_ag_0' in 'proc'.
(LNK-005)
Warning: Unable to resolve reference to 'data_ag_1' in 'proc'.
(LNK-005)
Warning: Unable to resolve reference to 'data_ag_2' in 'proc'.
(LNK-005)
Warning: Unable to resolve reference to 'data_ag_3' in 'proc'.
(LNK-005)
Creating black box for mac/mac...
Creating black box for alu/alu...
Creating black box for repeat_cntr/repeat_cntr...
Creating black box for dcmem/dcmem...
Creating black box for dmem/dmem...
Creating black box for fifo1/FIFO_top_0...
Creating black box for fifo0/FIFO_top_1...
Creating black box for mem_port0/mem_port...
Creating black box for dag3/data_ag_0...
Creating black box for dag2/data_ag_1...
Creating black box for dag1/data_ag_2...
Creating black box for dag0/data_ag_3...
Information: Issuing set_operating_conditions equivalent to
timing_propagate_single_condition_min_slew setting. (PTE-037)
set_operating_conditions -analysis_type on_chip_variation -library
[get_libs {typical.db:typical}]

Designs used to link proc:
<None>

Libraries used to link proc:
typical

 

[topgun]

Hi ,

try reading in the verilog files from the lowest module to the top
level module..
into synopsys and then see if the tool still complains about not
finding the modules..
and also in your link path...use '*' this will allow the tool to
search for all levels
of modules in the memory.....