Problem in Implementation Costraints

A

Atif

Guest
Hello all,
While synthesysing the verilog module to generate clock of 12.5MHz
from the default clock of XSA100 i.e 50MHz in ISE WebPack for
XC2S100-TQ144 Spartan-II FPGA, I am getting an error. I have two
inputs clock and reset and one output out.
Here I go step by step:

i) Synthesis verilog code
No error but the following warnings:
=========================================================================
* HDL Synthesis
*
=========================================================================

Synthesizing Unit <fulladd28>.
Related source file is ddfs.v.
WARNING:Xst:646 - Signal <sum<26>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<25>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<24>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<23>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<22>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<21>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<20>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<19>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<18>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<17>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<16>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<15>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<14>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<13>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<12>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<11>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<10>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<9>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<8>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<7>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<6>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<5>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<4>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<3>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<2>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<1>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<0>> is assigned but never used.
INFO:Xst:1304 - Contents of register <sum<27>> in unit <fulladd28>
never changes during circuit operation. The register is replaced by
logic.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <clock> is never used.
Unit <fulladd28> synthesized.
=========================================================================

ii) Implement design
works fine. But I am only seeing the signal out and not the clock and
reset in the Pad Reports.

iii) Constraining the Fit:
Create new Source (by right clicking on the verilog code
file)Implementation constraints file..

iv) Open Xilinx Pace by clicking "Assign package pin". It gives a
message
"Top Level Block has pins that are not connected to any signals. Do
you want them to treat them as user I/O?"
I click "Yes"

v) Then I assign the pins P93 to reset, P88 to clock, P67 to out. And
save it.

vi) Now when I click "Pad Report" to view the pin Assignment it gives
me the following error;
****************************************************************************
Annotating constraints to design from file "ddfs.ucf" ...
ERROR:NgdBuild:755 - Line 2 in 'ddfs.ucf': Could not find net(s)
'reset' in the
design. To suppress this error use the -aul switch, specify the
correct net
name or remove the constraint.
ERROR:NgdBuild:756 - Line 3 in 'ddfs.ucf': Could not find net(s)
'reset' in the
design. To suppress this error specify the correct net name or
remove the
constraint.
ERROR:NgdBuild:755 - Line 6 in 'ddfs.ucf': Could not find net(s)
'clock' in the
design. To suppress this error use the -aul switch, specify the
correct net
name or remove the constraint.
ERROR:NgdBuild:756 - Line 7 in 'ddfs.ucf': Could not find net(s)
'clock' in the
design. To suppress this error specify the correct net name or
remove the
constraint.
ERROR:parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"ddfs.ucf".

Writing NGDBUILD log file "fulladd28.bld"...
ERROR: NGDBUILD failed
Reason:

Completed process "Translate".
*******************************************************************************

here is the verilog code:
*******************************************************************************
`timescale 1ns/1ps
module fulladd28(out,clock,reset);
parameter a=28'd67108864;
parameter w = 28; // bit width of phase accumulator
output out;
input clock, reset;
reg [w-1:0] sum;
always @(posedge clock or posedge reset)
if(reset)
sum <= 0;
else
sum <= +a;
assign out = sum[w-1];
endmodule //end of module fulladd28
*******************************************************************************


Can anyone please guide me why is the error and how to remove it?
Sorry for bothering such a massy e-mail.

Thanks and Regards
Atif
Research Associate
 
The clue is in the Warnings from your synthesis tool. (You did READ them
before you posted them?) This isn't a C compiler - every warning is there
for a reason and must be justified. The warnings are telling you that you
have a mistake in the Verilog which means sum is never used, and will
therefore be optimised away, and that in turn leaves the clock and reset
redundent, which are duely deleted by the synthesis tool.

Have you tried simulating this design? You should have a free copy of
Modelsim with the Xilinx tools.

Verilog does not have the increment operators that C does. ie sum++ and
sum+=1 do not work in Verilog. Also, sum = +a simply sets sum to a. I think
you meant sum = sum + a;

Why are you using a 28 bit counter to divide a clock by four? Given that the
first 26 bits of 'd67108864 are zero, how about a two bit counter? How about
using the Spartan-II DLLs? Do you really want two clock domains? How about
clocking everything at 50MHz and use a clock enable?

--
Ian Poole, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


"Atif" <atif@kics.edu.pk> wrote in message
news:6a0a3f23.0311050119.315cbcef@posting.google.com...
Hello all,
While synthesysing the verilog module to generate clock of 12.5MHz
from the default clock of XSA100 i.e 50MHz in ISE WebPack for
XC2S100-TQ144 Spartan-II FPGA, I am getting an error. I have two
inputs clock and reset and one output out.
Here I go step by step:

i) Synthesis verilog code
No error but the following warnings:
=========================================================================
* HDL Synthesis
*
=========================================================================

Synthesizing Unit <fulladd28>.
Related source file is ddfs.v.
WARNING:Xst:646 - Signal <sum<26>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<25>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<24>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<23>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<22>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<21>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<20>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<19>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<18>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<17>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<16>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<15>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<14>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<13>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<12>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<11>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<10>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<9>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<8>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<7>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<6>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<5>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<4>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<3>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<2>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<1>> is assigned but never used.
WARNING:Xst:646 - Signal <sum<0>> is assigned but never used.
INFO:Xst:1304 - Contents of register <sum<27>> in unit <fulladd28
never changes during circuit operation. The register is replaced by
logic.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <clock> is never used.
Unit <fulladd28> synthesized.
=========================================================================

ii) Implement design
works fine. But I am only seeing the signal out and not the clock and
reset in the Pad Reports.

iii) Constraining the Fit:
Create new Source (by right clicking on the verilog code
file)Implementation constraints file..

iv) Open Xilinx Pace by clicking "Assign package pin". It gives a
message
"Top Level Block has pins that are not connected to any signals. Do
you want them to treat them as user I/O?"
I click "Yes"

v) Then I assign the pins P93 to reset, P88 to clock, P67 to out. And
save it.

vi) Now when I click "Pad Report" to view the pin Assignment it gives
me the following error;

****************************************************************************
Annotating constraints to design from file "ddfs.ucf" ...
ERROR:NgdBuild:755 - Line 2 in 'ddfs.ucf': Could not find net(s)
'reset' in the
design. To suppress this error use the -aul switch, specify the
correct net
name or remove the constraint.
ERROR:NgdBuild:756 - Line 3 in 'ddfs.ucf': Could not find net(s)
'reset' in the
design. To suppress this error specify the correct net name or
remove the
constraint.
ERROR:NgdBuild:755 - Line 6 in 'ddfs.ucf': Could not find net(s)
'clock' in the
design. To suppress this error use the -aul switch, specify the
correct net
name or remove the constraint.
ERROR:NgdBuild:756 - Line 7 in 'ddfs.ucf': Could not find net(s)
'clock' in the
design. To suppress this error specify the correct net name or
remove the
constraint.
ERROR:parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"ddfs.ucf".

Writing NGDBUILD log file "fulladd28.bld"...
ERROR: NGDBUILD failed
Reason:

Completed process "Translate".

****************************************************************************
Click to expand...
***
here is the verilog code:

****************************************************************************
Click to expand...
***
`timescale 1ns/1ps
module fulladd28(out,clock,reset);
parameter a=28'd67108864;
parameter w = 28; // bit width of phase accumulator
output out;
input clock, reset;
reg [w-1:0] sum;
always @(posedge clock or posedge reset)
if(reset)
sum <= 0;
else
sum <= +a;
assign out = sum[w-1];
endmodule file://end of module fulladd28

****************************************************************************
Click to expand...
***
Can anyone please guide me why is the error and how to remove it?
Sorry for bothering such a massy e-mail.

Thanks and Regards
Atif
Research Associate
Click to expand...
 
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