problem in delaying the input bit??

[dcreddy1980]

i have to delay the input data(X) by some number of clock periods depending
up on the signal tmp.

architecture behaviour of test
signal tmp : integer := 3;
signal clcokperiod : time := 2 ns;
begin
Y <= X after tmp*clockperiod; ---so, the o/p is obtained after 6 ns
end behaviour;
X and Y are bits(STD_LOGIC).i dont want to have the above code...because i
am setting the clock period on my own..could any one help me in getting the
same behaviour in a different way.

thanks in advance
dcreddy

 

If you are setting the clock period then you might be having clock as
the input, so use temp as a counter to count that many clock cycles and
make X<=Y.

Neo

 

[dcreddy1980]

hi...

entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;
architecture behaviour of test is
signal tmp : integer :=3;
signal clock period : time := 2 ns;
begin
Y <= X after tmp * clock period;
end behaviour;

u have to get the same behaviour as the above component does but not by
using after statement in the code for delaying the inout data.

 

[dcreddy1980]

hi...

entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;
architecture behaviour of test is
signal tmp : integer :=3;
signal clock period : time := 2 ns;
begin
Y <= X after tmp * clock period;
end behaviour;

u have to get the same behaviour as the above component does but not by
using after statement in the code for delaying the inout data.

 

[dcreddy1980]

Hello mike..

could u elaborate u r answer..with a code

regards,
dcreddy1980

 

[dcreddy1980]

Hello mike..

could u elaborate u r answer..with a code

regards,
dcreddy1980

 

[Mike Treseler]

dcreddy1980 wrote:

entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;
architecture behaviour of test is
signal tmp : integer :=3;
signal clock period : time := 2 ns;
begin
Y <= X after tmp * clock period;
end behaviour;

u have to get the same behaviour as the above component does but not by
using after statement in the code for delaying the inout data.

Consider a shift register.

-- Mike Treseler