Guest
Hello all !
Please see the codes given below, just compile them and coonect them as
per the following connectivity :
----------------------------------------------------------------------------
clock and reset are the only inputs.
clock16x16:
out_clk => flag_intr of (interlvr_behav)
count_ext => to all count_ext inputs
rom_data_behav:
Q => syst_data of (interlvr_behav)
rom_interlvr_interlvr
Q => PN_seq_index of (interlvr_behav)
----------------------------------------------------------------------------
There are in all 4 codes.
(1)clock16x16 ----------> is just a simple control block
(2)rom_data_behav -------> supplies a 16 bit data for test purpose.
(3)rom_interlvr_interlvr ----> just an indexing data provider
(4)interleaver_behav ------> is the block where my problem exists.
Here, I want to make array's hold_seq1 and hold_seq2
according
to index given by the signal count_ext. The zero'th element in the
array hold_seq1 misses the value !!! and the sequence
coming from syst_data does not get filled up correctly.
So what I want is that the locations from 0 to 13 of array hold_seq
sould have the 0 to 13 value as in the rom_data_behav,
while locations 14 and 15 of hold_seq should have value coming from the
fr_in_ser i.e.
hold_seq(0) <= syst_data0
hold_seq(1) <= syst_data1
hold_seq(1) <= syst_data2
.
.
.
hold_seq(13) <= syst_data13 <<--------********
hold_seq(14) <= fr_in_ser
hold_seq(15) <= fr_in_seR
RATHER, THE THING HAPPENING IS !!!
hold_seq(0) <= LAST LATCHED VALUE FROM rom_data_behav AT THE TIME OF
RESET
hold_seq(1) <= syst_data0
hold_seq(1) <= syst_data1
.
.
.
hold_seq(13) <= syst_data12 <<--------*********its 12 thought it shd
be 13
hold_seq(14) <= fr_in_ser
hold_seq(15) <= fr_in_ser
What is going wrong ?? why the corresponding syst_data is not giving
value to the 0th element of array hold_seq ???
----------@@@@@@@@@@@@ start of clock16x16 @@@@@---------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY clock16x16 IS
PORT(
clk : IN std_logic;
reset : IN std_logic;
count_ext: out natural range 15 downto 0;
count_bus : out std_logic_vector(3 downto 0);
out_clk : OUT std_logic
);
END clock16x16 ;
ARCHITECTURE arch_clock16x16 OF clock16x16 IS
BEGIN
-----------------------------------------
p0: process(reset,clk)
variable clk_var : std_logic;
variable count : natural range 0 to 31;
variable cnt : natural range 0 to 15;
begin
if rising_edge(clk) then
if reset='1' then
clk_var :='0';
count:=0;
cnt:=0;
count_ext <= cnt; ----- removing previous latched value
else
if count <= 15 then
clk_var :='0' ;
else
clk_var :='1' ;
end if;
------------------------------------------
out_clk <= clk_var;
count_bus <= CONV_STD_LOGIC_VECTOR(cnt,4);
count_ext <= cnt; ------- common count to all blocks
------------------------------------------
if count=31 then
count:=0;
else
count:=count +1;
end if;
-------------------------------
if cnt=15 then
cnt:=0;
else
cnt:=cnt +1;
end if;
-------------------------------
end if;
end if;
end process;
-----------------------------------------
END arch_clock16x16;
-----------@@@@@@@@@@@ end of clock16x16 @@@@@---------
-----@@@@@ start of rom_data_behav @@@@@@@@@@@@@@@---
library IEEE;
use IEEE.std_logic_1164.all;
entity rom_data_behav is
port (
--ADDRESS : in integer range 0 to 15;
Q : out std_logic;
CLK : in std_logic;
count_ext: in natural range 15 downto 0;
reset: in std_logic
);
end entity;
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture rom_data_behav_arch of rom_data_behav is
begin
process(CLK,reset)
variable clk_var : std_logic;
variable count : natural range 0 to 15;
variable ADDRESS_var : natural range 0 to 15;
begin
if rising_edge(CLK) then
if reset='1' then
-----I think here is one of the problem!!!
----- How to make count_ext=0 at the reset='1' ??
else
case (count_ext) is
when 0 => Q <= '1';
when 1 => Q <= '1';
when 2 => Q <= '1';
when 3 => Q <= '0';
when 4 => Q <= '1';
when 5 => Q <= '1';
when 6 => Q <= '0';
when 7 => Q <= '1';
when 8 => Q <= '1';
when 9 => Q <= '1';
when 10 => Q <= '0';
when 11 => Q <= '1';
when 12 => Q <= '0';
when 13 => Q <= '1';
when 14 => Q <= '0';
when 15 => Q <= '0';
when others => Q <= '0';
end case;
end if; -------end RESET
end if; -------end CLOCK
end process;
end architecture;
-----------@@@@@@@@@@@@@@ end of rom_data_behav @@@@@@@@@@---
-----------@@@@@@ start of rom_interlvr_interlvr @@@@@@@@@@
library IEEE;
use IEEE.std_logic_1164.all;
entity rom_interlvr_interlvr is
port (
--ADDRESS : in integer range 0 to 15;
Q : out integer range 0 to 15;
CLK : in std_logic;
reset: in std_logic;
count_ext: in natural range 15 downto 0; ---external counter
index : out integer
);
end entity;
--}} End of automatically maintained section
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture rom_interlvr_interlvr_arch of rom_interlvr_interlvr is
begin
process(CLK,reset) ---------------------
begin
if rising_edge(CLK) then
if reset='1' then
else
case (count_ext) is
when 0 => Q <= 9;
when 1 => Q <= 5;
when 2 => Q <= 14;
when 3 => Q <= 3;
when 4 => Q <= 1;
when 5 => Q <= 6;
when 6 => Q <= 11;
when 7 => Q <= 2;
when 8 => Q <= 15;
when 9 => Q <= 4;
when 10 => Q <= 8;
when 11 => Q <= 10;
when 12 => Q <= 0;
when 13 => Q <= 12;
when 14 => Q <= 13;
when 15 => Q <= 7;
when others => Q <= 0;
end case;
end if; -------end RESET
end if; -------end CLOCK
end process;
end architecture;
------@@@@@@@@@@@@ end of rom_interlvr_interlvr----@@@@@@@@@@@@@@@@
-----------@@@@@@@@@@@@@ start interleaver_behav @@@@@@@---------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity interleaver_behav is
port(
fr_in_ser : in STD_LOGIC;
syst_data : in std_logic ;
PN_seq_index: in integer;
clk : in STD_LOGIC;
count_ext: in natural range 15 downto 0; ----common counter
reset : in STD_LOGIC;
flag_intr : in std_logic;------DUAL selection
intrlvr_out : out STD_LOGIC
);
end interleaver_behav;
--}} End of automatically maintained section
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture arch_interleaver_behav of interleaver_behav is
signal hold_seq1 : std_logic_vector(15 downto 0);
signal hold_seq2 : std_logic_vector(15 downto 0); ----DUAL
begin
process(clk,reset)
variable cnt : integer range 15 downto 0 ; -----redundant
begin
-----------------------------------------------
if rising_edge(clk) then
if (reset= '1') then
hold_seq1 <= "0000000000000000"; ---initial is zero
hold_seq2 <= "0000000000000000";
intrlvr_out <= '0';
--cnt:=0;
else
-------------------------DUAL frame selection----------
if (flag_intr = '0') then ----frame 1 selection
case count_ext is
when 14 => hold_seq1(count_ext)<= fr_in_ser; --"Trellis
terminated" bit
when 15 => hold_seq1(count_ext)<= fr_in_ser; --"Trellis
terminated" bit
when others => hold_seq1(count_ext) <= syst_data;
end case;
else --------------------frame 2 selection
case count_ext is
when 14 => hold_seq2(count_ext)<= fr_in_ser; ---"Trellis
terminated" bit
when 15 => hold_seq2(count_ext)<= fr_in_ser; ---"Trellis
terminated" bit
when others => hold_seq2(count_ext) <= syst_data;
end case;
end if;
--------------------Interleaving
start-----------------------------------
if (flag_intr = '0') then
intrlvr_out <= hold_seq2(PN_seq_index);
else
intrlvr_out <= hold_seq1(PN_seq_index);
end if;
---------------------END interlaving---------------------------------
end if; ------end RESET
end if; ----- end CLOCK
end process;
end arch_interleaver_behav;
-----------@@@@@@@@@@@@ end of interleaver_behav @@@@@@@@@@@@@-------
Please see the codes given below, just compile them and coonect them as
per the following connectivity :
----------------------------------------------------------------------------
clock and reset are the only inputs.
clock16x16:
out_clk => flag_intr of (interlvr_behav)
count_ext => to all count_ext inputs
rom_data_behav:
Q => syst_data of (interlvr_behav)
rom_interlvr_interlvr
Q => PN_seq_index of (interlvr_behav)
----------------------------------------------------------------------------
There are in all 4 codes.
(1)clock16x16 ----------> is just a simple control block
(2)rom_data_behav -------> supplies a 16 bit data for test purpose.
(3)rom_interlvr_interlvr ----> just an indexing data provider
(4)interleaver_behav ------> is the block where my problem exists.
Here, I want to make array's hold_seq1 and hold_seq2
according
to index given by the signal count_ext. The zero'th element in the
array hold_seq1 misses the value !!! and the sequence
coming from syst_data does not get filled up correctly.
So what I want is that the locations from 0 to 13 of array hold_seq
sould have the 0 to 13 value as in the rom_data_behav,
while locations 14 and 15 of hold_seq should have value coming from the
fr_in_ser i.e.
hold_seq(0) <= syst_data0
hold_seq(1) <= syst_data1
hold_seq(1) <= syst_data2
.
.
.
hold_seq(13) <= syst_data13 <<--------********
hold_seq(14) <= fr_in_ser
hold_seq(15) <= fr_in_seR
RATHER, THE THING HAPPENING IS !!!
hold_seq(0) <= LAST LATCHED VALUE FROM rom_data_behav AT THE TIME OF
RESET
hold_seq(1) <= syst_data0
hold_seq(1) <= syst_data1
.
.
.
hold_seq(13) <= syst_data12 <<--------*********its 12 thought it shd
be 13
hold_seq(14) <= fr_in_ser
hold_seq(15) <= fr_in_ser
What is going wrong ?? why the corresponding syst_data is not giving
value to the 0th element of array hold_seq ???
----------@@@@@@@@@@@@ start of clock16x16 @@@@@---------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY clock16x16 IS
PORT(
clk : IN std_logic;
reset : IN std_logic;
count_ext: out natural range 15 downto 0;
count_bus : out std_logic_vector(3 downto 0);
out_clk : OUT std_logic
);
END clock16x16 ;
ARCHITECTURE arch_clock16x16 OF clock16x16 IS
BEGIN
-----------------------------------------
p0: process(reset,clk)
variable clk_var : std_logic;
variable count : natural range 0 to 31;
variable cnt : natural range 0 to 15;
begin
if rising_edge(clk) then
if reset='1' then
clk_var :='0';
count:=0;
cnt:=0;
count_ext <= cnt; ----- removing previous latched value
else
if count <= 15 then
clk_var :='0' ;
else
clk_var :='1' ;
end if;
------------------------------------------
out_clk <= clk_var;
count_bus <= CONV_STD_LOGIC_VECTOR(cnt,4);
count_ext <= cnt; ------- common count to all blocks
------------------------------------------
if count=31 then
count:=0;
else
count:=count +1;
end if;
-------------------------------
if cnt=15 then
cnt:=0;
else
cnt:=cnt +1;
end if;
-------------------------------
end if;
end if;
end process;
-----------------------------------------
END arch_clock16x16;
-----------@@@@@@@@@@@ end of clock16x16 @@@@@---------
-----@@@@@ start of rom_data_behav @@@@@@@@@@@@@@@---
library IEEE;
use IEEE.std_logic_1164.all;
entity rom_data_behav is
port (
--ADDRESS : in integer range 0 to 15;
Q : out std_logic;
CLK : in std_logic;
count_ext: in natural range 15 downto 0;
reset: in std_logic
);
end entity;
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture rom_data_behav_arch of rom_data_behav is
begin
process(CLK,reset)
variable clk_var : std_logic;
variable count : natural range 0 to 15;
variable ADDRESS_var : natural range 0 to 15;
begin
if rising_edge(CLK) then
if reset='1' then
-----I think here is one of the problem!!!
----- How to make count_ext=0 at the reset='1' ??
else
case (count_ext) is
when 0 => Q <= '1';
when 1 => Q <= '1';
when 2 => Q <= '1';
when 3 => Q <= '0';
when 4 => Q <= '1';
when 5 => Q <= '1';
when 6 => Q <= '0';
when 7 => Q <= '1';
when 8 => Q <= '1';
when 9 => Q <= '1';
when 10 => Q <= '0';
when 11 => Q <= '1';
when 12 => Q <= '0';
when 13 => Q <= '1';
when 14 => Q <= '0';
when 15 => Q <= '0';
when others => Q <= '0';
end case;
end if; -------end RESET
end if; -------end CLOCK
end process;
end architecture;
-----------@@@@@@@@@@@@@@ end of rom_data_behav @@@@@@@@@@---
-----------@@@@@@ start of rom_interlvr_interlvr @@@@@@@@@@
library IEEE;
use IEEE.std_logic_1164.all;
entity rom_interlvr_interlvr is
port (
--ADDRESS : in integer range 0 to 15;
Q : out integer range 0 to 15;
CLK : in std_logic;
reset: in std_logic;
count_ext: in natural range 15 downto 0; ---external counter
index : out integer
);
end entity;
--}} End of automatically maintained section
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture rom_interlvr_interlvr_arch of rom_interlvr_interlvr is
begin
process(CLK,reset) ---------------------
begin
if rising_edge(CLK) then
if reset='1' then
else
case (count_ext) is
when 0 => Q <= 9;
when 1 => Q <= 5;
when 2 => Q <= 14;
when 3 => Q <= 3;
when 4 => Q <= 1;
when 5 => Q <= 6;
when 6 => Q <= 11;
when 7 => Q <= 2;
when 8 => Q <= 15;
when 9 => Q <= 4;
when 10 => Q <= 8;
when 11 => Q <= 10;
when 12 => Q <= 0;
when 13 => Q <= 12;
when 14 => Q <= 13;
when 15 => Q <= 7;
when others => Q <= 0;
end case;
end if; -------end RESET
end if; -------end CLOCK
end process;
end architecture;
------@@@@@@@@@@@@ end of rom_interlvr_interlvr----@@@@@@@@@@@@@@@@
-----------@@@@@@@@@@@@@ start interleaver_behav @@@@@@@---------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity interleaver_behav is
port(
fr_in_ser : in STD_LOGIC;
syst_data : in std_logic ;
PN_seq_index: in integer;
clk : in STD_LOGIC;
count_ext: in natural range 15 downto 0; ----common counter
reset : in STD_LOGIC;
flag_intr : in std_logic;------DUAL selection
intrlvr_out : out STD_LOGIC
);
end interleaver_behav;
--}} End of automatically maintained section
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture arch_interleaver_behav of interleaver_behav is
signal hold_seq1 : std_logic_vector(15 downto 0);
signal hold_seq2 : std_logic_vector(15 downto 0); ----DUAL
begin
process(clk,reset)
variable cnt : integer range 15 downto 0 ; -----redundant
begin
-----------------------------------------------
if rising_edge(clk) then
if (reset= '1') then
hold_seq1 <= "0000000000000000"; ---initial is zero
hold_seq2 <= "0000000000000000";
intrlvr_out <= '0';
--cnt:=0;
else
-------------------------DUAL frame selection----------
if (flag_intr = '0') then ----frame 1 selection
case count_ext is
when 14 => hold_seq1(count_ext)<= fr_in_ser; --"Trellis
terminated" bit
when 15 => hold_seq1(count_ext)<= fr_in_ser; --"Trellis
terminated" bit
when others => hold_seq1(count_ext) <= syst_data;
end case;
else --------------------frame 2 selection
case count_ext is
when 14 => hold_seq2(count_ext)<= fr_in_ser; ---"Trellis
terminated" bit
when 15 => hold_seq2(count_ext)<= fr_in_ser; ---"Trellis
terminated" bit
when others => hold_seq2(count_ext) <= syst_data;
end case;
end if;
--------------------Interleaving
start-----------------------------------
if (flag_intr = '0') then
intrlvr_out <= hold_seq2(PN_seq_index);
else
intrlvr_out <= hold_seq1(PN_seq_index);
end if;
---------------------END interlaving---------------------------------
end if; ------end RESET
end if; ----- end CLOCK
end process;
end arch_interleaver_behav;
-----------@@@@@@@@@@@@ end of interleaver_behav @@@@@@@@@@@@@-------