problem for generating flatten cdl netlist

Guest
Hi, Folks,

I try to generate a flat cdl netlist for my schematic from icfb. In
my schematic, I have resistor which name is R22<0>, R22<1> ..........
When I use si -batch to generate flat cdl netlist, it give me the
following error:
( explain "Error in evaluating property value:
'ancNetlistFileInstOutput()'." probeType "instance" pathObjectName
"R22<1>" pathList "/Itstrcvr_bscell/Itstrcvr" probeArgType
"probeColor" )
( explain "Error in evaluating property value:
'ancNetlistFileInstOutput()'." probeType "instance" pathObjectName
"R22<0>" pathList "/Itstrcvr_bscell/Itstrcvr" probeArgType
"probeColor" )

When I use si -batch to generate hier cdl netlist, I got the perfect
cdl netlist.

I checked the si.env settings. The only difference between my flat
mode and hier mode is one setting difference:
cdlNetlistType ='fnl or cdlNetlistType ='hnl

Is there any settings I can use to solve the problem so I can generate
a flat cdl netlist?


Thanks a lot for your kind help.

Best,
singulaar
 
singulaar@gmail.com wrote, on 06/01/09 20:07:
Hi, Folks,

I try to generate a flat cdl netlist for my schematic from icfb. In
my schematic, I have resistor which name is R22<0>, R22<1> ..........
When I use si -batch to generate flat cdl netlist, it give me the
following error:
( explain "Error in evaluating property value:
'ancNetlistFileInstOutput()'." probeType "instance" pathObjectName
"R22<1>" pathList "/Itstrcvr_bscell/Itstrcvr" probeArgType
"probeColor" )
( explain "Error in evaluating property value:
'ancNetlistFileInstOutput()'." probeType "instance" pathObjectName
"R22<0>" pathList "/Itstrcvr_bscell/Itstrcvr" probeArgType
"probeColor" )

When I use si -batch to generate hier cdl netlist, I got the perfect
cdl netlist.

I checked the si.env settings. The only difference between my flat
mode and hier mode is one setting difference:
cdlNetlistType ='fnl or cdlNetlistType ='hnl

Is there any settings I can use to solve the problem so I can generate
a flat cdl netlist?


Thanks a lot for your kind help.

Best,
singulaar
Click to expand...
The only similar occurrence I could find for this was where the termOrder in the
CDF was incorrect. Not sure if that's the case for you.

Are you using a current version of the tools?

Probably the best thing is to contact Cadence customer support with a testcase
to reproduce the problem.

Best Regards,

Andrew.
 
On Jun 1, 2:30 pm, Andrew Beckett <andr...@DcEaLdEeTnEcTe.HcIoSm>
wrote:
singul...@gmail.com wrote, on 06/01/09 20:07:



Hi, Folks,

I try to generate a flat cdl netlist for my schematic from icfb. In
my schematic, I have resistor which name is R22<0>, R22<1> ..........
When I use si -batch to generate flat cdl netlist, it give me the
following error:
( explain "Error in evaluating property value:
'ancNetlistFileInstOutput()'." probeType "instance" pathObjectName
"R22<1>" pathList "/Itstrcvr_bscell/Itstrcvr" probeArgType
"probeColor" )
( explain "Error in evaluating property value:
'ancNetlistFileInstOutput()'." probeType "instance" pathObjectName
"R22<0>" pathList "/Itstrcvr_bscell/Itstrcvr" probeArgType
"probeColor" )

When I use si -batch to generate hier cdl netlist, I got the perfect
cdl netlist.

I checked the si.env settings. The only difference between my flat
mode and hier mode is one setting difference:
cdlNetlistType ='fnl or cdlNetlistType ='hnl

Is there any settings I can use to solve the problem so I can generate
a flat cdl netlist?

Thanks a lot for your kind help.

Best,
singulaar

The only similar occurrence I could find for this was where the termOrder in the
CDF was incorrect. Not sure if that's the case for you.

Are you using a current version of the tools?

Probably the best thing is to contact Cadence customer support with a testcase
to reproduce the problem.

Best Regards,

Andrew.
Click to expand...
Hi, Andrew,
Thanks a lot for your quick answer.

I used the latest version of cadence tool.

In the schematic, I build a resistance array by name one single
resistor "R22<3:0>", there are four resistor indside. I guess when I
do flatten, cadence tool couldn't identify it as a resistor array, but
nets connecting are all 4bit bus, so the tool thinks this is a
connectivity problem.

Thanks again.
Best,
Singulaar
 
singulaar wrote, on 06/03/09 18:39:
Hi, Andrew,
Thanks a lot for your quick answer.

I used the latest version of cadence tool.

In the schematic, I build a resistance array by name one single
resistor "R22<3:0>", there are four resistor indside. I guess when I
do flatten, cadence tool couldn't identify it as a resistor array, but
nets connecting are all 4bit bus, so the tool thinks this is a
connectivity problem.

Thanks again.
Best,
Singulaar
Click to expand...
How latest is "latest version"? What does Help->About say in the CIW?

I'm very surprised about this - I've not seen it before. I still think
contacting customer support with a testcase is your best avenue.

Regards,

Andrew.
 
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