problem about timing analysis in soc encounter

[phoenixson]

I have implemented the design on soc encounter 4.2,it can perform the timing
driven wroute and nanoroute smoothly,But when I do timing analysis Using the
embeded timing analysis tool,i found it maybe reported the wrong timing
information,in detail,many latches are involved in the design,so flip-flop
registers and latches mixed together,for instance,a low level latch followed
a rising-edge flip-flop register, and the flip-flop needs capture the output
data from the latch,then the timing delay calculation equation of timing
analysis tool is indicated below:
assumed the clock waveform {0 4},period is 8ns,skew is 0.3ns.
For latch delay:
T(arrival)=T(time given to start)+T(G->Q)+T(combinational delay)
So
T(arrival)=(4ns-0.3ns)+0.2ns+2.2ns=6.1ns
For flip-flop register required time:
T(required timg)=T(rising-edge arrival)-T(latch-enable
time)-T(skew)=8ns-4ns-0.3ns=3.7ns

so the violation time is 3.7ns-6.1ns=-2.4ns

why?? why it calculated like so?? i didnot know indeed.In fact,the time met
my requirement,the slack time is (3.7ns-(6.1ns-3.7ns))=1.3ns
Is it a bug of soc encounter?? pls explain it for me,thanks a lot.