Probléme with symplify synthetisis

O

Ouadid

Guest
Hi every body,
I tried to write some code in VHDL. In the fact all is going well in
the design process, the simulations are well done. Unfortunatly when i
try to synthetis my design i have some trouble. I'm using symplify
7.3.0 and i tried also leonardo spectrum. Both of them failed to
synthetise my design and they don't give any information about the
bug. This is a sample i'm using to show the bug:
******************************************************
Library ieee;
use ieee.std_logic_1164.all;
entity FIFO35_UP is
port(
clk, rst : in std_logic;
Ue1 : in std_logic_vector(3 downto 0);
Us1 : out std_logic_vector(3 downto 0)
);
end FIFO35_UP;
Architecture AFIFO35_UP of FIFO35_UP is
Type FIFO_tableauPU is array (4 downto 0) of std_logic_vector(3
downto 0);
signal fifoU1: FIFO_tableauPU;
Begin
process(clk) begin
--The problem is in the
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')
if(clk'event and
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')) then
if (rst='1') then
for i in fifoU1'range loop
fifoU1(i)<="0011";
end loop;
else
for i in fifoU1'high downto 1 loop
fifoU1(i)<=fifoU1(i-1);
end loop;
fifoU1(0)<=Ue1;
end if;
end if;
end process;
Us1<=fifoU1(4);
end;
***************************************************************
it's just a sample, and in the fact i nead to use the clue in order to
use an overloaded xor so the ieee.std_logic_1164 don't have to be
shown in the code.
Any help????
thanks
 
I don't think it is a bug in your design.
It seems that the synthesis tools you used do not support this
if (ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')) then

You could replace it with:
if clk'event and clk='1' then
or
if rising_edge(clk) then

Egbert Molenkamp


"Ouadid" <ouadid@iquebec.com> schreef in bericht
news:fdc8ff7f.0312101132.1a71db6f@posting.google.com...
Hi every body,
I tried to write some code in VHDL. In the fact all is going well in
the design process, the simulations are well done. Unfortunatly when i
try to synthetis my design i have some trouble. I'm using symplify
7.3.0 and i tried also leonardo spectrum. Both of them failed to
synthetise my design and they don't give any information about the
bug. This is a sample i'm using to show the bug:
******************************************************
Library ieee;
use ieee.std_logic_1164.all;
entity FIFO35_UP is
port(
clk, rst : in std_logic;
Ue1 : in std_logic_vector(3 downto 0);
Us1 : out std_logic_vector(3 downto 0)
);
end FIFO35_UP;
Architecture AFIFO35_UP of FIFO35_UP is
Type FIFO_tableauPU is array (4 downto 0) of std_logic_vector(3
downto 0);
signal fifoU1: FIFO_tableauPU;
Begin
process(clk) begin
--The problem is in the
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')
if(clk'event and
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')) then
if (rst='1') then
for i in fifoU1'range loop
fifoU1(i)<="0011";
end loop;
else
for i in fifoU1'high downto 1 loop
fifoU1(i)<=fifoU1(i-1);
end loop;
fifoU1(0)<=Ue1;
end if;
end if;
end process;
Us1<=fifoU1(4);
end;
***************************************************************
it's just a sample, and in the fact i nead to use the clue in order to
use an overloaded xor so the ieee.std_logic_1164 don't have to be
shown in the code.
Any help????
thanks
Click to expand...
 
Hi Egbert,
It is the same conclusion i made. The synthesis tools support just
a subset of the VHDL langage and unfortunatly i used the bad one. I'll
have to rewrite some of my design without the subtlety of operators
overloading. If i do that it will be impossible for me to call the
ieee.std_logic_1164.all; library in my file.
I tried also to use a global clk and reset that i added in my own
library with a function that uses the clk'event and clk='1', but this
subset is not supported either.
Do any one tried to synthetisis such code with more luck than
me???? if so, what is the tool you used???
Thanks for all
 
Ouadid,
It seems you are making your life more difficult
than it needs to be.

When you start to look at the details of this statement
it gets even more interesting:
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')

Note, "=" is not explicitly defined by std_logic_1164.
In fact, I don't believe it is overloaded explicitly
anywhere. So I wonder if the LRM requires a compliant
tool to be able to reference an implicit operator
this way. It may not be a tool bug.

If I understand right, you are doing this so you can
use your own version of the XOR function that uses
std_logic or std_logic_vector on its inputs.

The conclusion that I have reached is that it is
troublesome to overload an operator in such a way
that creates a homograph with the overloading in one
of the standard packages. I recommend that you
consider writing your own XOR function with a different
name (MY_XOR) and calling it as a function rather
than an operator.

Cheers,
Jiml


Ouadid wrote:

Hi every body,
I tried to write some code in VHDL. In the fact all is going well in
the design process, the simulations are well done. Unfortunatly when i
try to synthetis my design i have some trouble. I'm using symplify
7.3.0 and i tried also leonardo spectrum. Both of them failed to
synthetise my design and they don't give any information about the
bug. This is a sample i'm using to show the bug:
******************************************************
Library ieee;
use ieee.std_logic_1164.all;
entity FIFO35_UP is
port(
clk, rst : in std_logic;
Ue1 : in std_logic_vector(3 downto 0);
Us1 : out std_logic_vector(3 downto 0)
);
end FIFO35_UP;
Architecture AFIFO35_UP of FIFO35_UP is
Type FIFO_tableauPU is array (4 downto 0) of std_logic_vector(3
downto 0);
signal fifoU1: FIFO_tableauPU;
Begin
process(clk) begin
--The problem is in the
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')
if(clk'event and
ieee.std_logic_1164."="(clk,ieee.std_logic_1164.'1')) then
if (rst='1') then
for i in fifoU1'range loop
fifoU1(i)<="0011";
end loop;
else
for i in fifoU1'high downto 1 loop
fifoU1(i)<=fifoU1(i-1);
end loop;
fifoU1(0)<=Ue1;
end if;
end if;
end process;
Us1<=fifoU1(4);
end;
***************************************************************
it's just a sample, and in the fact i nead to use the clue in order to
use an overloaded xor so the ieee.std_logic_1164 don't have to be
shown in the code.
Any help????
thanks
Click to expand...
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Thanks Jim for the advises,
I take a look to the std_logic_1164 and there is no "=" operator
for an std_logic. I think they are using the one that is described in
the std_logic_arith or may be the std_logic_unsigned. Any way i'll
change my mind and keep my design as simple as possible and for that
i'll use the first way i did it, with my own function (MY_XOR) rather
than overloading the XOR.
But i have a last question. I tried this approach because it's
not very nice to have a code like this sample:
s<=MY_XOR(MY_XOR(X,Y),MY_XOR(Z,T));
I find it more easy to overload an operator in order to have something
like:
s<=X XOR Y XOR Z XOR T;
it's not for the fun but it's more easy to be automatically generated
with a coregen that is wrote in C. Any nice idea???? i read so many
books and surf over the net without result.
PS: Sorry for my english but you guess it i think i'm more at ease in
french:)
Thanks
 
Ouadid,
I take a look to the std_logic_1164 and there is no "=" operator
for an std_logic.
With your reference methodology, the only "=" that it cna be using is
Click to expand...
the implicitly defined one that is associated with std_logic.
In fact for std_logic, I think this is the only "=" that exists.
Note, it may be correct to reference it this way. It may also
be an area where the standard is silent and some tools do it
one way and other tools do it another. Anyone know? Otherwise
later I will have to do some LRM reading.

I find it more easy to overload an operator in order to have something
like:
s<=X XOR Y XOR Z XOR T;
Click to expand...
First note that the above is an XOR reduce operation.
If you want a bit type (like std_logic), then
write an xor_reduce function and call it by:
s<= XOR_REDUCE(X & Y & Z & T) ; -- xor reduce defined for std_logic_vector

For arrays (std_logic_vector), it is not so easy to do
this because we don't have unconstrained arrays of
arrays (yet).

Why are you overloading XOR? Are you doing something
other than XOR? Note, in general, VHDL requires that
non-associative logic operators have parentheses
in the expression. The current implementation of XOR,
AND, and OR are associative, so no parenthese are
required. It would be bad to overload XOR and for
it not to be associative.

I have having trouble at guessing what you need to do.
In general to create a new meaning for an operator that
does not collide with anything, you need to create a new
type. See numeric_std for an example (where they created
the types unsigned and signed). Some how I sense, this
is not exactly what you want either though.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Thank you Jim for ur help, i appeciate a lot.
I'll rewrite my code without using this kind of overloading. I
think it wasn't a good idea. I'll write a basic function and overload
it in order to keep my design as simple as possible.
Sincerely
Ouadid
 
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