Primitive JK flip flop

[nezhate]

Hi all,
i'm newer to the verilog world, i have to model a negative
edge-triggered JK flipflop, jk_ff with asynchronous preset and clear as
a UDP. q = 1 when preset = 1 and q = 0 when clear = 1.
The problem is when J=K=1 the next ouput(q+) must be = not(q), but
after testing with ICARUS VERILOG i get x.
also: when J=K=0 the next output (q+) must be = (q) = unchanged, but
the execution gives x.
Can you tell me why it doesn't work correctly?
Thanks for all.

Here's the code that i've used:

primitive JK_ff(q,clear,preset,clk,j,k);
output q;
reg q;
input clear,preset,clk,j,k;
initial
q=0;
table
//clear preset clk j k : q : q+;
1 0 ? ? ? : ? : 0;
0 1 ? ? ? : ? : 1;
0 0 (10) 0 1 : ? : 0;
0 0 (10) 1 0 : ? : 1;
0 0 (10) 0 0 : ? : -; // in this case i got q=x,
expected q+ = q
0 0 (10) 1 1 : 0 : 1; //in this case i got q=x, expected
q+ = 1
0 0 (10) 1 1 : 1 : 0; //is it wright this code ?
endtable
endprimitive // JK_ff

 

[Alexey Kulentsov]

Hi all!

I wrote simple module. Idea the next: when button is pressed, counter
resets to zero and RESET signal activated. After counting to 127 counter
stops and RESET deactivated.

---------------------------------------------------------------

module resetFormer(clk, button, out);

input clk, button;
output out;

reg[7:0] dereg=0;

assign out=dereg[7];

always @(negedge clk)
if(dereg[7]==0)
dereg=dereg+1;

always @(negedge button) dereg=0;


endmodule
---------------------------------------------------------------


For this module I have WARNING:Xst:647 - Input <button> is never used.
When I look into RTL schematics I see 'out' signal connected direct to
ground.

That I am doing wrong?

BTW, if I exchange always blocks, I get two warnings - about clk and
button unused.

 

[Art Stamness]

dereg = 0 ;

Xst may interpret that as dereg always being 0, and therefore ignore
all later assignments. I don't believe that is legal verilog even.

try :

reg[7:0] dereg ;

And you will have to deal with the fact, in simulation, that the
register value will startup with X.

And do yourself a favor, when modeling registers *ALWAYS* use <= (
non-blocking assignment) to avoid race conditions during simulation.

-Art

 

[Alexey Kulentsov]

Art Stamness wrote:

dereg = 0 ;


Xst may interpret that as dereg always being 0, and therefore ignore
all later assignments. I don't believe that is legal verilog even.
As minimum in Xilinx this is o.k.

try :

reg[7:0] dereg ;

And you will have to deal with the fact, in simulation, that the
register value will startup with X.

And do yourself a favor, when modeling registers *ALWAYS* use <= (
non-blocking assignment) to avoid race conditions during simulation.

Thanks for your comments, I remove initialization and change = to <=
but no luck: no any difference in result.

---------------------------------------------------
module resetFormer(clk, button, out);

input clk, button;
output out;

reg[7:0] dereg;

assign out=dereg[7];

always @(negedge clk)
if(dereg[7]==0)
dereg <= dereg+1;

always @(negedge button) dereg <= 0;

endmodule
---------------------------------------------------

 

Art Stamness wrote:

dereg = 0 ;

Xst may interpret that as dereg always being 0, and therefore ignore
all later assignments. I don't believe that is legal verilog even.

It is legal in Verilog-2001, where it means the same thing as

reg [7:0] dereg;
initial dereg = 0;

I don't know what xst will think of that, but most synthesis tools
don't like initial blocks.

 

[John_H]

<sharp@cadence.com> wrote in message
news:1126303890.949116.277280@g44g2000cwa.googlegroups.com...

Art Stamness wrote:
reg[7:0] dereg = 0 ;

Xst may interpret that as dereg always being 0, and therefore ignore
all later assignments. I don't believe that is legal verilog even.

It is legal in Verilog-2001, where it means the same thing as

reg [7:0] dereg;
initial dereg = 0;

I don't know what xst will think of that, but most synthesis tools
don't like initial blocks.

I understand XST does a decent job with these but some optimizations might
"break" with the init value, specifically one long register used in a shift
that could be implemented in an SRL had a register broken out at each bit
that was initialized high rather than giving a good init value to a full
SRL.

reg [15:0] MyRotate = 16'h0109;
always @(posedge clk) MyRotate <= {MyRotate[14:0],MyRotate[15]};

The above code should ideally produce one SRL with a 16-bit init value.