prflatten problem

[rstevesat]

Actually i am making a custom layout for a 8 bit multiplier .I made a
schematic for the multiplier and want to export the def to soc
encounter ,before that i tried for prflatten .
I have got 3 views for halfadder ,fulladder and AND gate used in my
schematic : functional -containing verilog description , symbol -
containing he symbol and layout view .
Now when i do the prflatten it reports that all symbol views have
changed when last extracted . Please give a slolution.

 

[S. Badel]

Dear rstevesat,
your problem is with switch/stop view expansion. to make it short, you need
to have abstract or autoAbstract view at some point in your hierarchy.
more specifically, prflatten will recursively examinate you design
schematics, until it finds abstract or autoAbstract view for all and every
component.

layout will not be suitable as stopping view unless it contains all properties
needed for exporting a valid def (see design data translator).
the simplest way would be to use abstract generator (tools->abstract in virtuoso)
to generate abstracts.

cheers,
stéphane


rstevesat wrote:

Actually i am making a custom layout for a 8 bit multiplier .I made a
schematic for the multiplier and want to export the def to soc
encounter ,before that i tried for prflatten .
I have got 3 views for halfadder ,fulladder and AND gate used in my
schematic : functional -containing verilog description , symbol -
containing he symbol and layout view .
Now when i do the prflatten it reports that all symbol views have
changed when last extracted . Please give a slolution.