Preventing timing warnings

[agb]

I'm running some large ModelSim gate level timing simulations whic
simulate asynchronous inputs coming in through a metastability protecte
input. The simulation is giving large numbers of timing violation warning
for these inputs which are expected but unwanted for these input gat
instances.
Does anyone know how I can suppress timing set up and hold warnings fo
specific instances only?



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[HT-Lab]

"agb" <andy.bradford@n_o_s_p_a_m.ultra-ccs.com> wrote in message
news:qM2dncyECLMdRg3RnZ2dnUVZ_qydnZ2d@giganews.com...

I'm running some large ModelSim gate level timing simulations which
simulate asynchronous inputs coming in through a metastability protected
input. The simulation is giving large numbers of timing violation warnings
for these inputs which are expected but unwanted for these input gate
instances.
Does anyone know how I can suppress timing set up and hold warnings for
specific instances only?

If you are running Modelsim SE or Questa you can use the
tcheck_set/tcheck_status command (see Reference manual)

Hans
www.ht-lab.com

 

[John McCaskill]

On Sep 15, 9:43 am, "agb" <andy.bradford@n_o_s_p_a_m.ultra-ccs.com>
wrote:

I'm running some large ModelSim gate level timing simulations which
simulate asynchronous inputs coming in through a metastability protected
input. The simulation is giving large numbers of timing violation warnings
for these inputs which are expected but unwanted for these input gate
instances.
Does anyone know how I can suppress timing set up and hold warnings for
specific instances only?

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

You did not mention which brand of FPGA you are using. For Xilinx, you
can use the ASYNC_REG constraint on your synchronizing registers. I
know that it stops the propagation of 'X's when the input timing is
violated and I believe that it also suppresses the warnings.

See the Xilinx constraint guide for all the details.

Regards,

John McCaskill
www.FasterTechnology.com

 

[agb]

"agb" <andy.bradford@n_o_s_p_a_m.ultra-ccs.com> wrote in message
news:qM2dncyECLMdRg3RnZ2dnUVZ_qydnZ2d@giganews.com...
I'm running some large ModelSim gate level timing simulations which
simulate asynchronous inputs coming in through a metastabilit
protected
input. The simulation is giving large numbers of timing violatio
warnings
for these inputs which are expected but unwanted for these input gate
instances.
Does anyone know how I can suppress timing set up and hold warnings for
specific instances only?

If you are running Modelsim SE or Questa you can use the
tcheck_set/tcheck_status command (see Reference manual)

Hans
www.ht-lab.com


Thanks, but unfortunately I'm running ModelSim PE and implementing on a

Actel ProAsic Plus FPGA


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[Muzaffer Kal]

On Fri, 17 Sep 2010 02:56:22 -0500, "agb"
<andy.bradford@n_o_s_p_a_m.n_o_s_p_a_m.ultra-ccs.com> wrote:

"agb" <andy.bradford@n_o_s_p_a_m.ultra-ccs.com> wrote in message
news:qM2dncyECLMdRg3RnZ2dnUVZ_qydnZ2d@giganews.com...
I'm running some large ModelSim gate level timing simulations which
simulate asynchronous inputs coming in through a metastability
protected
input. The simulation is giving large numbers of timing violation
warnings
for these inputs which are expected but unwanted for these input gate
instances.
Does anyone know how I can suppress timing set up and hold warnings for
specific instances only?

If you are running Modelsim SE or Questa you can use the
tcheck_set/tcheck_status command (see Reference manual)

Hans
www.ht-lab.com


Thanks, but unfortunately I'm running ModelSim PE and implementing on an
Actel ProAsic Plus FPGA

Then another option is to edit the SDF file and zero out the
setup/hold values for the specific instances you have in mind.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com