preprocessor to expand for-loop?

[Dong Huang]

I am looking for a reliable preprocessor to expand all for-loops in
RTL code. Does anybody know whether there's such an existing tool?

The reason is that I feel hard to debug with for-loop in RTL, since
only the last iteration can be annotated with value, in a common debug
tools like Verdi or DVE.

 

[glen herrmannsfeldt]

Dong Huang <dhuang.simplnano@gmail.com> wrote:

< I am looking for a reliable preprocessor to expand all for-loops in
< RTL code. Does anybody know whether there's such an existing tool?

The PL/I preprocessor might be able to do it. I can't think of
anything in verilog that it wouldn't, though I have never tried
it and never thought to try it.

If I work on a design that needs such, I sometimes write an
AWK program to generate the required verilog.

< The reason is that I feel hard to debug with for-loop in RTL, since
< only the last iteration can be annotated with value, in a common debug
< tools like Verdi or DVE.

Well, I started in verilog before the for loop was added...

-- glen

 

[Poojan Wagh]

On Aug 21, 2:44 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Dong Huang <dhuang.simpln...@gmail.com> wrote:

I am looking for a reliable preprocessor to expand all for-loops in
RTL code.  Does anybody know whether there's such an existing tool?

The PL/I preprocessor might be able to do it.  I can't think of
anything in verilog that it wouldn't, though I have never tried
it and never thought to try it.

If I work on a design that needs such, I sometimes write an
AWK program to generate the required verilog.

The reason is that I feel hard to debug with for-loop in RTL, since
only the last iteration can be annotated with value, in a common debug
tools like Verdi or DVE.

Well, I started in verilog before the for loop was added...

-- glen

I've thought about using m4 to do such a thing. In the end, I just
wrote a python* program to spit out what I wanted.

* Substitute your favorite interactive language.

--
Poojan

 

[glen herrmannsfeldt]

Poojan Wagh <poojanwagh@gmail.com> wrote:

Dong Huang <dhuang.simpln...@gmail.com> wrote:

I am looking for a reliable preprocessor to expand all for-loops in
RTL code. ?Does anybody know whether there's such an existing tool?

(then I wrote)

The PL/I preprocessor might be able to do it. ?I can't think of
anything in verilog that it wouldn't, though I have never tried
it and never thought to try it.
(snip)

<> I've thought about using m4 to do such a thing. In the end, I just
<> wrote a python* program to spit out what I wanted.

<> * Substitute your favorite interactive language.

Yes. It might not be so hard to write a program in such a language
that would actually do the processing, though.

-- glen

 

[Jonathan Bromley]

On Fri, 21 Aug 2009 00:03:43 -0700 (PDT), Dong Huang wrote:

I am looking for a reliable preprocessor to expand all for-loops in
RTL code. Does anybody know whether there's such an existing tool?

Yes; it's called a "Verilog simulator". Sorry to be so negative,
but you simply can't do this with a preprocessor. Your loops
may have bounds that depend on parameters, and you cannot know
the values of those parameters until the entire Verilog
hierarchy has been elaborated. Preprocessors will get
that sort of thing badly wrong unless they replicate the
whole Verilog elaboration process.

The reason is that I feel hard to debug with for-loop in RTL, since
only the last iteration can be annotated with value, in a common debug
tools like Verdi or DVE.

But if you discover the whole for-loop misbehaving, surely you
can then look at it closely using single-stepping or suchlike?
--
Jonathan Bromley, Consultant

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