Preprocessing in Verilog

J

Joe

Guest
Hi all,

Long time ago when I learn C, it was not allowed to put comments
after a #define statement. For example, the following statements
will fail in some old C compiler because the comments are included
as part of macro ABC:

#define ABC 123 // My test value
....
printf("%d\n", ABC);

This is now allowed to put the comment after #define in most modern
C compilers. But how about Verilog? Any Verilog compiler/simulator
could fail with this kind of coding? e.g. Is the following code allowed
in all Verilog tools?

`define ABC 123 // My test value

Thanks

Joe
 
Joe wrote:

Hi all,

Long time ago when I learn C, it was not allowed to put comments
after a #define statement. For example, the following statements
will fail in some old C compiler because the comments are included
as part of macro ABC:

#define ABC 123 // My test value
...
printf("%d\n", ABC);

This is now allowed to put the comment after #define in most modern
C compilers. But how about Verilog? Any Verilog compiler/simulator
could fail with this kind of coding? e.g. Is the following code allowed
in all Verilog tools?

`define ABC 123 // My test value

Thanks

Joe
I can't speak for all Verilog tools, but that's perfectly legal Verilog. The
macro definition ends at //. From the Verilog IEEE 1364-1995 LRM:

"If a one-line comment (that is, a comment speciŢed with the characters //)
is included in the text, then the comment
shall not become part of the substituted text."

Arjuna
 
Arjuna Wijesurendra wrote:
I can't speak for all Verilog tools, but that's perfectly legal Verilog. The
macro definition ends at //. From the Verilog IEEE 1364-1995 LRM:

"If a one-line comment (that is, a comment speciŢed with the characters //)
is included in the text, then the comment
shall not become part of the substituted text."

Arjuna
Thanks Arjuna :cool:
If the LRM specified this is allowed then it shouldn't be a
problem for me then. (If customers can't compile it because of this,
it is their tool's fault ;-)

Joe
 

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