Preferred method of sending encrypted Verilog IP

[Edward Arthur]

Hi,

We want to simulate a vendors design with our design.
They require the design be encrypted.

I can think of three ways:

a.) Mangling/obfuscating the code (weak), e.g. using "vcs -Xman=NUM"
b.) `protect/`endprotect
c.) Synopsys' Verilog Model Compiler

Am I missing any other methods?

What is the recommended method?

Thanks,
/Ed

 

[Petter Gustad]

earthur@attbi.com (Edward Arthur) writes:

We want to simulate a vendors design with our design.
They require the design be encrypted.

I can think of three ways:

a.) Mangling/obfuscating the code (weak), e.g. using "vcs -Xman=NUM"
b.) `protect/`endprotect

I don't know if this has changed over the years, but a script which
would let you break this scheme was posted on the net a few years ago.

c.) Synopsys' Verilog Model Compiler

This is probably the best method. But it's OS/architecture dependent
and expensive.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Anil Dalwani]

ncprotect / Cadence IP Protection that is available in latest release
of Cadence tools.

Let me know if you need more information.
-Anil

Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<m3llrur9on.fsf@scimul.dolphinics.no>...

earthur@attbi.com (Edward Arthur) writes:

We want to simulate a vendors design with our design.
They require the design be encrypted.

I can think of three ways:

a.) Mangling/obfuscating the code (weak), e.g. using "vcs -Xman=NUM"
b.) `protect/`endprotect

I don't know if this has changed over the years, but a script which
would let you break this scheme was posted on the net a few years ago.

c.) Synopsys' Verilog Model Compiler

This is probably the best method. But it's OS/architecture dependent
and expensive.

Petter

 

[Eyck Jentzsch]

Anil Dalwani wrote:

ncprotect / Cadence IP Protection that is available in latest release
of Cadence tools.

Let me know if you need more information.
-Anil

Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<m3llrur9on.fsf@scimul.dolphinics.no>...

earthur@attbi.com (Edward Arthur) writes:


We want to simulate a vendors design with our design.
They require the design be encrypted.

I can think of three ways:

a.) Mangling/obfuscating the code (weak), e.g. using "vcs -Xman=NUM"
b.) `protect/`endprotect

I don't know if this has changed over the years, but a script which
would let you break this scheme was posted on the net a few years ago.


c.) Synopsys' Verilog Model Compiler

This is probably the best method. But it's OS/architecture dependent
and expensive.

Petter

Or 'Affirma Model Packager' (AMP), available since NCSim/LDV Version 3

-Eyck

 

[Ira]

A bit belated, but you might be interested
in source code obfuscation tools that are
independent of vendor's synthesis tools.
See http://www.semanticdesigns.com/Products/Obfuscators/VerilogObfuscator.html.

 

[Ira]

A bit belated, but you might be interested
in source code obfuscation tools that are
independent of vendor's synthesis tools.
See http://www.semanticdesigns.com/Products/Obfuscators/VerilogObfuscator.html.