predictable timing for xilinx cpld?

[guille]

Hi all,

I'm looking at a design based on a xilinx XCR3256XL cpld. Signals come
from different devices (e.g. a CPU), go through the cpld, and end on
the system's expansion bus. I need to derive the timings for all the
signals on this expansion bus, which depend on the timing of the
signals at the CPU and on the prop. delays of the cpld.

The datasheet says this device has "predictable and deterministic
timing". What does this mean exactly? For example, take the pad to pad
delay, which is specified to be 10 ns for the -10 part. Is this 10 ns
a maximum value, or can I rely in the delay being 10 ns?

e.g. take the following signal from the CPU:

CE0# assert delay from rising edge of CLK: min 2 ns, typ 8 ns, max 10
ns.

The CLK signal does not go through the cpld, but CE0# does. The timing
report indeed says propagation delay for CE0# is 10 ns. Can I assume
that CE0# at the expansion bus has min 12 ns, typ 18 ns, max 20 ns
relative to the rising edge of CLK? Or are the figures specified by
xilinx _maximum_ times only?

Thanks.