Precision Synthesis is optimizing away my code - AHHH!

Hey everyone,

I'm using Precision Synthesis and i want to stop it optimizing some
code that results in shared registers being used, say for example
where i have a 32 bit register initialized on reset to all 1's it's
being replaced by a single register set to 1 shared 32 times. These
registers are just assigned to all 1's for a default as they are later
populated with data read from memory.

The subsequent assignment of data read from memory to these registers
seems to be ignored.

I tried placing "//pragma attribute assertion_checker_machine
resource_sharing false" in the module but it didnt seem to affect it.

There probably is some other issue at play here but if i can rule out
the synthesis tool being the problem then i can confirm it's my dodgy
code! :-O

Cheers!

Rob.

 

[Mike Treseler]

robquigley@gmail.com wrote:

I'm using Precision Synthesis and i want to stop it optimizing some
code that results in shared registers being used, say for example
where i have a 32 bit register initialized on reset to all 1's it's
being replaced by a single register set to 1 shared 32 times. These
registers are just assigned to all 1's for a default as they are later
populated with data read from memory.

I would run a sim to see why this is not happening.

The subsequent assignment of data read from memory to these registers
seems to be ignored.

Or they aren't described correctly.

There probably is some other issue at play here but if i can rule out
the synthesis tool being the problem then i can confirm it's my dodgy
code! :-O

I wouldn't blame synthesis until
I had a working sim on a synchronous design.


-- Mike Treseler

 

[Jonathan Bromley]

On Tue, 1 Jul 2008 15:06:47 -0700 (PDT), robquigley@gmail.com wrote:

Hey everyone,

I'm using Precision Synthesis and i want to stop it optimizing some
code that results in shared registers being used, say for example
where i have a 32 bit register initialized on reset to all 1's it's
being replaced by a single register set to 1 shared 32 times. These
registers are just assigned to all 1's for a default as they are later
populated with data read from memory.

The subsequent assignment of data read from memory to these registers
seems to be ignored.

It's likely that the synth tool has been able to prove that the
register can never be written. The most common reason for this
is that your register address is too narrow, so that some of
the higher-numbered registers are unreachable. Dodgy code
can play its part too, sadly Has this happened to *all*
your registers, or just some? Try to identify what features
the "optimised-away" registers share: do they all have a
certain address bit set?

Stupid question: have you yet run a simulation in which you
can see the offending registers being updated?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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