pre+post layout simulation

[Salvatore Callea]

Hallo everybody,

I've a vhdl module:

entity M is
generic (I : integer := 0);
port (
A : in std_logic;
-- pragma translate_off
B : in std_logic;
-- pragma translate_on
C : out std_logic
);
end M;

the entity I get from synthesizer is the following:

entity M is
port (
A : in std_logic;
C : out std_logic
);
end M;

If I've instantiated this block inside a testbench, the only
ways I found to use the same testbench for pre and post layout
simulation were been:
1) Adding omitted "signals" and "generics" to the entity from synthesizer
before compiling
2) Writing
two different architecture and
two different configuration for the testbench entity,
simulating the configuration for pre layout or for post layout
simulation
as I need
3) Using a "generic" conditioned "generate" clause to instantiate
a port map for pre layout and another for post layout simulation
as I need.

Do you know any other way to simulate pre and post layout module
using the same testbench with one architecture,
declaring and instantiating only one component valid both for pre
and post layout module,
without changing post layout module before compiling?

Thanks in advance
Salvatore