practical Virtex2 output buffer speeds

[Robert Sefton]

Is it documented anywhere what the practical upper limits are, in terms of Mbps, for the various Virtex2 output buffer
types? For example, if I need to output a 600MHz clock (effectively 1.2Gbps), do I need to use LVDS or HSTL, or can a
FAST 3.3V CMOS output buffer handle it? I don't have the luxury of running HSpice sims, but can I extract this
information from any of the buffer models available from Xilinx?

Thanks,

Robert

 

[Austin Lesea]

Robert,

You can run an IBIS simulator.......

By the way, I found out today that there is a public domain software
tool that converts IBIS back into spice, so you could then run the IBIS
model under a spice simulator that doesn't already support IBIS (like a
public domain spice program).

So as to not frustrate you if you just don't have any tool available
right now, and are in a position to have to make a decision, our hotline
can run "what if" cases if you tell them the IO standard(s) you want to
use, the frequency, the trace length, and the load (as in another Xilinx
part, or 10 pF, or whatever).

Finally, if you can't even wait that long to get the right answer, my
own experience in the lab tells me that for very light loading, and
short run lengths (like less than 6 ") if everything is done right as
far as signal integrity engineering goes:

Virtex II, single ended IO - 200 MHz (HSTL 1.8V); differential IO - 420
MHz LVDS
Virtex II Pro, single ended IO - 266 MHz (HSTL 1.8V); differential IO -
420 MHz LVDS
Virtex 4, single ended - TBD (can't say right now, looks too good);
differential - 500 MHz LVDS

Your mileage may vary depending on loading, etc.

My numbers are for the commercial operating range, and all speed grades
(as IO does not vary by speed grade much at all).

Austin

Robert Sefton wrote:

Is it documented anywhere what the practical upper limits are, in terms of Mbps, for the various Virtex2 output buffer
types? For example, if I need to output a 600MHz clock (effectively 1.2Gbps), do I need to use LVDS or HSTL, or can a
FAST 3.3V CMOS output buffer handle it? I don't have the luxury of running HSpice sims, but can I extract this
information from any of the buffer models available from Xilinx?

Thanks,

Robert

 

[Robert Sefton]

Thanks, Austin. Not the answer I was hoping for, but I'll figure something out. When will CML be available as a SelectIO
option? Virtex 4?

Robert

"Austin Lesea" <austin@xilinx.com> wrote in message news:cerkj2$p2b2@cliff.xsj.xilinx.com...

Robert,

You can run an IBIS simulator.......

By the way, I found out today that there is a public domain software
tool that converts IBIS back into spice, so you could then run the IBIS
model under a spice simulator that doesn't already support IBIS (like a
public domain spice program).

So as to not frustrate you if you just don't have any tool available
right now, and are in a position to have to make a decision, our hotline
can run "what if" cases if you tell them the IO standard(s) you want to
use, the frequency, the trace length, and the load (as in another Xilinx
part, or 10 pF, or whatever).

Finally, if you can't even wait that long to get the right answer, my
own experience in the lab tells me that for very light loading, and
short run lengths (like less than 6 ") if everything is done right as
far as signal integrity engineering goes:

Virtex II, single ended IO - 200 MHz (HSTL 1.8V); differential IO - 420
MHz LVDS
Virtex II Pro, single ended IO - 266 MHz (HSTL 1.8V); differential IO -
420 MHz LVDS
Virtex 4, single ended - TBD (can't say right now, looks too good);
differential - 500 MHz LVDS

Your mileage may vary depending on loading, etc.

My numbers are for the commercial operating range, and all speed grades
(as IO does not vary by speed grade much at all).

Austin

Robert Sefton wrote:
Is it documented anywhere what the practical upper limits are, in terms of Mbps, for the various Virtex2 output
buffer
types? For example, if I need to output a 600MHz clock (effectively 1.2Gbps), do I need to use LVDS or HSTL, or can
a
FAST 3.3V CMOS output buffer handle it? I don't have the luxury of running HSpice sims, but can I extract this
information from any of the buffer models available from Xilinx?

Thanks,

Robert

 

[Robert Sefton]

Thanks, Austin. Not the answer I was hoping for, but I'll figure something out. When will CML be available as a SelectIO
option? Virtex 4?

Robert

"Austin Lesea" <austin@xilinx.com> wrote in message news:cerkj2$p2b2@cliff.xsj.xilinx.com...

Robert,

You can run an IBIS simulator.......

By the way, I found out today that there is a public domain software
tool that converts IBIS back into spice, so you could then run the IBIS
model under a spice simulator that doesn't already support IBIS (like a
public domain spice program).

So as to not frustrate you if you just don't have any tool available
right now, and are in a position to have to make a decision, our hotline
can run "what if" cases if you tell them the IO standard(s) you want to
use, the frequency, the trace length, and the load (as in another Xilinx
part, or 10 pF, or whatever).

Finally, if you can't even wait that long to get the right answer, my
own experience in the lab tells me that for very light loading, and
short run lengths (like less than 6 ") if everything is done right as
far as signal integrity engineering goes:

Virtex II, single ended IO - 200 MHz (HSTL 1.8V); differential IO - 420
MHz LVDS
Virtex II Pro, single ended IO - 266 MHz (HSTL 1.8V); differential IO -
420 MHz LVDS
Virtex 4, single ended - TBD (can't say right now, looks too good);
differential - 500 MHz LVDS

Your mileage may vary depending on loading, etc.

My numbers are for the commercial operating range, and all speed grades
(as IO does not vary by speed grade much at all).

Austin

Robert Sefton wrote:
Is it documented anywhere what the practical upper limits are, in terms of Mbps, for the various Virtex2 output
buffer
types? For example, if I need to output a 600MHz clock (effectively 1.2Gbps), do I need to use LVDS or HSTL, or can
a
FAST 3.3V CMOS output buffer handle it? I don't have the luxury of running HSpice sims, but can I extract this
information from any of the buffer models available from Xilinx?

Thanks,

Robert

 

[Allan Herriman]

On Wed, 04 Aug 2004 14:32:06 -0700, Austin Lesea <austin@xilinx.com>
wrote:

By the way, I found out today that there is a public domain software
tool that converts IBIS back into spice, so you could then run the IBIS
model under a spice simulator that doesn't already support IBIS (like a
public domain spice program).

Hi Austin,

Could you please post a link to this tool?

Thanks,
Allan.

 

[Symon]

Robert,
The Xilinx LVDS inputs include 2.5V CML signals in their common mode range,
just about. Use a resistor pack or two if you're worried! A lot of CML parts
also have wide common mode range inputs that can handle the Xilinx LVDS
output signals. Check out parts from Micrel and ONsemi.
CML has the problem, like PECL, that the output is referred to Vcc. As the
geometry shrinks in FPGAs, it's harder to support 3.3V. 5V is already dead.
Xilinx have 90nm triple-oxide technology which mitigates some of these
problems, but I'd be very impressed if they build a CML and an LVDS output
on the same pair of IOBs. The Rocket I/Os with their specialist IOs are one
way round the problem.
I'd love to see Xilinx make a super-fast FPGA with the fabric based on CML.
It would only need to be the size of an old 3020, but could open up a world
of possibilities at gigabit rates, when use alongside a large conventional
FPGA.
Cheers, Syms.
"Robert Sefton" <rsefton@nextstate.com> wrote in message
news:2ndhdhFvc98vU1@uni-berlin.de...

Thanks, Austin. Not the answer I was hoping for, but I'll figure something
out. When will CML be available as a SelectIO
option? Virtex 4?

Robert