Power supply enquiry on PKS and Silicon Ensemble

[Chayut Kongsavatsak]

Hi All,
I am now using PKS synthesis tool to synthesise my VHDL codes and obtain
..v file to do place & route in Silicon Ensemble.

Please let me explain what I have done so far and I will ask for some
suggestions at the end of this e-mail.

There are two designs (Purely Digital and both Analogue & Digital) that
I want to synthesise and then do place & route.

1. Purely Digital
Note: Top-level design has the input called "Din(3 downto 0)" and the
output called "Dout(3 downto 0)"

In PKS, after I synthesised the code and inserted pads for inputs and
outputs, I obtained the .v file.

I then go on using this .v file and import it to Silicon Ensemble.
Because the pads have been inserted to the input and output within PKS,
I can see that those pads are displayed in Silicon Ensemble with another
two extra pads for Power (VDD) and Ground (GND). I am happy with this
result.

But

My problems come when I want to place & route the design that has both
analogue (such as Analogue to Digital Converter) and digital (VHDL) part.

Let me choose an ADC as the example for my analogue part. The ADC
consists of analogue circuit (Transistor Level) and digital Circuit
(Std. Cell level). The inputs and outputs pin for this ADC are as follows.

1. A_VDD -- Analogue Power
2. A_GND -- Analogue Ground
3. D_VDD -- Digital Power
4. D_GND -- Digital Ground
5. A_In -- Anaogue Input
6. D_Out(3:0) -- 4-bit digital Output

I then create the component that represents this ADC in VHDL and use
port map to connect this component to the Digital (VHDL) part in
Top-level (VHDL). Since the output of the ADC (D_out(3:0)) is connected
to the input of the Digital Part (Din(3 downto 0)), the input and
outputs of the top-level are as follows.

1. A_VDD -- Analogue Power (Input)
2. A_GND -- Analogue Ground (Input)
3. D_VDD -- Digital Power (Input)
4. D_GND -- Digital Ground (Input)
5. A_In -- Analogue Input
6. Dout(3 downto 0) -- 4-bit digital Output from the Digital Part

After I synthesised the top-level and VHDL codes, PKS will create a
black box for the ADC. I then inserted pads for inputs and output in the
same way like what I have done in Purely digital approach. The .v file
is then obtained.

If I import this .v file to Silicon Ensemble, the following pads are
displayed

1. A_VDD -- Analogue Power (Input)
2. A_GND -- Analogue Ground (Input)
3. D_VDD -- Digital Power (Input)
4. D_GND -- Digital Ground (Input)
5. A_In -- Anaogue Input
6. Dout(3 downto 0) -- 4-bit digital Output from the Digital Part

And the extra two pads for Digital Part

7. VDD -- Power for Digital Part
8. GND -- Ground for Digital Part


As you can see, the D_VDD which is the power for the digital part in the
ADC can be connected to VDD of the VHDL part, and also D_GND to GND.

My questions are

How can I connect D_VDD and VDD together and also D_GND to GND? So there
are only two pins for the power and ground of the Digital Part (both ADC
and VHDL part) insteading of having 4 pins (D_VDD, A_GND, VDD and GND).

Should this be done in PKS or Silicon Ensemble?

Should the component represeting the ADC have D_VDD and D_GND pins?

How can I specify that A_VDD, A_GND, and A_In are analogue pads? Again,
should this be done in PKS or Silicon Ensemble?


I would be very grateful if anyone could give some suggestions


Thank you very much,
Chayut