Power plane assignments in a Xilinx PCI card

[Dan DeConinck]

Hello ,

I was looking at someone else's ( 4 layer ) design and I noticed that they
had the ground plane on layer two: ( I always have ground on LAYER 3 )

LAYER 1 = component
LAYER 4 = solder side

Well , does the layer assignment matter ? ( in terms of noise or impedance
.... )

Here is an idea. If ground is on layer two then the signals on layer 1 might
be more isolated from noise in the power plane on layer 3, ( note: I have
almost all signals routed on layer 1; layer 4 is almost bare )

Is that a real benefit ?

Would the ground plane have noise too ? I always think of the ground plane
as being clean and the power plane as having the noise but perhaps this is a
false notion ?

Also should the power and ground planes extend down into the PCI bus edge
connector fingers ? Or is that a rather insignificant concern one way or the
other.

Sincerely Dan

 

[Martin Euredjian]

Here is an idea. If ground is on layer two then the signals on layer 1
might
be more isolated from noise in the power plane on layer 3,

The problem is much more complicated than this. There is no such thing as
"isolation". Keep that in mind. You could have a badly designed ground
layer right below your signal layer and make a mess out of the whole thing.
Also, operating frequencies and signal standards are important.

Think "return path" for every single signal. Try to visualize how current
will be delivered to the chip in question. Then to the pin driving a trace.
And from the pin to the. Which is a capacitor that needs to be
charged --among other things. And then discharged. The return path is
important. At high speeds power delivery to the chip can be (it is usually
the goal) localized by means of small decoupling capacitors and inter-plane
energy storage. At lower frequencies energy can be delivered from farther
out.

Would the ground plane have noise too ? I always think of the ground plane
as being clean and the power plane as having the noise but perhaps this is
a
false notion ?

Absolutely. "Ground" is a product of our imagination. Pick a spot. Call
it your reference. I can pick a different one. Probably just as valid.
Current flowing through a conductor will result in resistive and inductive
effects. Capacitive effects are added when many conductors are in close
proximity. This means that the "ground" layer will have different
potentials at different point at different times. The ground layer can
actually oscillate and resonate. Imagine 200 pins switching form low to
high in unison in 1ns at the far end (w/respect to the power connector) of
the board. Bad things can happen. This is why the SI community resorts to
fancy simulation tools.

Also should the power and ground planes extend down into the PCI bus edge
connector fingers ? Or is that a rather insignificant concern one way or
the
other.

How would you get power into the board otherwise? Are you saying that you'd
run a trace from the PCI edge connector's power/gnd pins into the
power/ground planes? No. The planes need to go everywhere.

You might want to pickup a good high-speed design book (Howard Johnson's
"High Speed Digital Design, a Handbook of Black Magic") and/or search the
WWW for articles on the subject.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[Matt]

I would add this one to Martin's recommendation. (I've read both.)

http://www.speedingedge.com/rtft_book.htm

Matt



"Dan DeConinck" <pixelsmart@sympatico.ca> wrote in message
news:0szMb.6213$881.755369@news20.bellglobal.com...

Hello ,

I was looking at someone else's ( 4 layer ) design and I noticed that they
had the ground plane on layer two: ( I always have ground on LAYER 3 )

LAYER 1 = component
LAYER 4 = solder side

Well , does the layer assignment matter ? ( in terms of noise or
impedance
... )

Here is an idea. If ground is on layer two then the signals on layer 1
might
be more isolated from noise in the power plane on layer 3, ( note: I have
almost all signals routed on layer 1; layer 4 is almost bare )

Is that a real benefit ?

Would the ground plane have noise too ? I always think of the ground plane
as being clean and the power plane as having the noise but perhaps this is
a
false notion ?

Also should the power and ground planes extend down into the PCI bus edge
connector fingers ? Or is that a rather insignificant concern one way or
the
other.

Sincerely Dan