Power-on reset

Is there a dedicated power-on reset function in Verilog? What I want to
achieve is that my own reset functionality will be executed when the
FPGA (Xilinx Spartan3/400) undergoes power-on reset.

Maybe power-on reset is available as a Xilix core, but I haven't been
able to find anything like that.

I was hoping to avoid external POR circuitry.


Thanks,

Borge

 

[Borge]

Thanks Ray,

but
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0373_357.html
says the ROC is used for VHDL simulation, not for Verilog or synthesis.


I was perhaps a bit unclear. The power-on-reset is something I will
need for synthesis. I wonder if the Xilinx part has a power-on
detection circuit with a logical output that I could OR with my (active
high) reset input.

I don't mind the gates resetting to '0', but I'm using some random
number generators that have constant, nonzero seeds set up in my code.

Regards,
Břrge


Ray Andraka wrote

Xilinx comes up in a programmable known state. You can instantiate the
ROC primitive to make your design take advantage of it (unless
explicitly told otherwise, all the flip-flops come up cleared).

 

[Slurp]

"Borge" <borge.strand@gmail.com> wrote in message
news:1163352825.751658.268890@k70g2000cwa.googlegroups.com...
Thanks Ray,

but
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0373_357.html
says the ROC is used for VHDL simulation, not for Verilog or synthesis.

I was perhaps a bit unclear. The power-on-reset is something I will
need for synthesis. I wonder if the Xilinx part has a power-on
detection circuit with a logical output that I could OR with my (active
high) reset input.

I don't mind the gates resetting to '0', but I'm using some random
number generators that have constant, nonzero seeds set up in my code.

Regards,
Břrge

+++++++++++++++++++++++++++++++++++++++++++++++

As all the FPGA's FF's are reset to zero on powerup, why not create a
counter that inhibits itself after reaching a suitable a preset value when
clocked with one of your system clocks?
Use the terminal count decode as your POR (adjusting polarity as
appropriate).


Slurp

 

[Borge]

Good idea!

Or perhaps even better, have a register with no reset value be counted
up towards a preset and let the local reset be active between preset
one and preset two. After reaching preset two there's no more counting.


If we can KNOW that the register is reset to either 0xFF or 0x00, and
not the preset values, this should generate a local reset pulse.

So, for example, a 4-bit register could count up from 0 (or F) to 2,
activate reset, count to 4 and then deactivate reset and stop counting.


I love your abbreviations, but how would you declare the 4-bit register
in practical, synthesizable Verilog?


Thanks,
Borge



Slurp skrev:> As all the FPGA's FF's are reset to zero on powerup, why
not create a

counter that inhibits itself after reaching a suitable a preset value when
clocked with one of your system clocks?
Use the terminal count decode as your POR (adjusting polarity as
appropriate).


Slurp