Power-On-Reset from a xilinx

[Tullio Grassi]

I'd like to use my Virtex2 to generate an off-chip power-on-reset,
for other devices on the board.
I thought about bringing the internal GSR signal to a pin, but
Xilinx support (Case # 503734) said it's impossible.

I am thinking about a state machine like that:

Start --> POR --> Stop

that will remain in "Stop" forever.
I am worried about illegal transitions/states creating a mess
on the board. Comments ?
--
Tullio Grassi

=====================================
Univ. of Maryland-Dept. of Physics |
College Park, MD 20742 - US |
Tel +1 301 405 5970 |
Fax +1 301 699 9195 |
======================================

 

[Martin Euredjian]

Well, if you initialize the flip-flops through the bitmap you'll know that
they'll wake-up in a given state. For example, in Verilog:

reg outgoing_rst = 1'b1;

You can use FPGA Editor to verify that the FF in question is set to the
desired value in the bitfile.

This also applies to a counter you may want to use to time the
assertion/de-assertion of the signal:

reg [11:0] rst_counter = 12'b0;

With this you know how that module will start from a fresh bitfile load.
The remaining logic isn't very difficult and should be pretty reliable. For
example, you could increment the counter with one of the clocks and stop
incrementing when the MSB is "1". You'd use a case statement to fire off
different events during the power-on reset cycle. You can even add a warm
boot feature by having other logic reset the counter during operation.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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where
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"Tullio Grassi" <tgrassi@cut_here.mail.cern.ch> wrote in message
newsine.LNX.4.44.0311022103250.23452-100000@lxplus020.cern.ch...

I'd like to use my Virtex2 to generate an off-chip power-on-reset,
for other devices on the board.
I thought about bringing the internal GSR signal to a pin, but
Xilinx support (Case # 503734) said it's impossible.

I am thinking about a state machine like that:

Start --> POR --> Stop

that will remain in "Stop" forever.
I am worried about illegal transitions/states creating a mess
on the board. Comments ?
--
Tullio Grassi

=====================================
Univ. of Maryland-Dept. of Physics |
College Park, MD 20742 - US |
Tel +1 301 405 5970 |
Fax +1 301 699 9195 |
======================================

 

[Simon Peacock]

I would suggest that you use a proper reset chip to reset the FPGA and then
you can use a simple machine to generate resets going out.

FPGA's have always been a little problematic starting up in my experience I
believe that its due to the power supply dipping .. never been proved but
the always work floorlessly with a clean reset. (rather than floorless .. as
in bottomless pit)

Simon


"Tullio Grassi" <tgrassi@cut_here.mail.cern.ch> wrote in message
newsine.LNX.4.44.0311022103250.23452-100000@lxplus020.cern.ch...

I'd like to use my Virtex2 to generate an off-chip power-on-reset,
for other devices on the board.
I thought about bringing the internal GSR signal to a pin, but
Xilinx support (Case # 503734) said it's impossible.

I am thinking about a state machine like that:

Start --> POR --> Stop

that will remain in "Stop" forever.
I am worried about illegal transitions/states creating a mess
on the board. Comments ?
--
Tullio Grassi

=====================================
Univ. of Maryland-Dept. of Physics |
College Park, MD 20742 - US |
Tel +1 301 405 5970 |
Fax +1 301 699 9195 |
======================================

 

[Amontec Team, Laurent Gau]

Please look Xilinx website, there are good advice about the reset system.

You can do proper reset signal inside the FPGA. If you have an onboard
FPGA, you don't need to add a expensive external reset chip.

You can generate a synchronous reset signal inside your FPGA and drive
external rst from your synchronous reset.

Laurent
www.amontec.com


Simon Peacock wrote:

I would suggest that you use a proper reset chip to reset the FPGA and then
you can use a simple machine to generate resets going out.

FPGA's have always been a little problematic starting up in my experience I
believe that its due to the power supply dipping .. never been proved but
the always work floorlessly with a clean reset. (rather than floorless .. as
in bottomless pit)

Simon


"Tullio Grassi" <tgrassi@cut_here.mail.cern.ch> wrote in message
newsine.LNX.4.44.0311022103250.23452-100000@lxplus020.cern.ch...

I'd like to use my Virtex2 to generate an off-chip power-on-reset,
for other devices on the board.
I thought about bringing the internal GSR signal to a pin, but
Xilinx support (Case # 503734) said it's impossible.

I am thinking about a state machine like that:

Start --> POR --> Stop

that will remain in "Stop" forever.
I am worried about illegal transitions/states creating a mess
on the board. Comments ?
--
Tullio Grassi

=====================================
Univ. of Maryland-Dept. of Physics |
College Park, MD 20742 - US |
Tel +1 301 405 5970 |
Fax +1 301 699 9195 |
======================================