Power nets in Xilinx FPGAs

[fpgalover]

I have a design implemented on a Xilinx Virtex 5. The design contains several power nets sourced by TIEOFFs and feeding some of the slices used by the design. A closer look at several of the LUT equations with a power net input, shows that the power net input does not actually affect the output of the LUT

For example, assuming two nets are feeding a slice. One of the nets is a power net feeding input A6, while the other net is feeding input A1. The LUT equation could be something like the following
<A6LUT>=(A6+~A6)*(A2
What is confusing to me is the fact that (A6+~A6) is always true, thus should not affect the output of the LUT

My questions is, why is a power net needed in that case
Thanks,

 

[Allan Herriman]

On Fri, 18 Feb 2011 09:58:19 -0600, fpgalover wrote:

I have a design implemented on a Xilinx Virtex 5. The design contains
several power nets sourced by TIEOFFs and feeding some of the slices
used by the design. A closer look at several of the LUT equations with a
power net input, shows that the power net input does not actually affect
the output of the LUT.

For example, assuming two nets are feeding a slice. One of the nets is a
power net feeding input A6, while the other net is feeding input A1. The
LUT equation could be something like the following:
A6LUT>=(A6+~A6)*(A2)
What is confusing to me is the fact that (A6+~A6) is always true, thus
should not affect the output of the LUT.

If you model the LUT as an ideal device that behaves according to its
truth table, then indeed the "unused" inputs have no effect on the output.

But LUTs are more like rams: they don't implement logic functions with
gates. Instead, they look up answers based on an address you supply, and
they use all of their inputs to form that address regardless of the
contents of the truth table.

Regards,
Allan