Power estimation

[Sathyanarayan B]

Hi,
Can someone suggest me how to estimate power at RTL level?

For some reason, the previous messages that I had posted have not
appeared in this webpage.

Satya

 

[glen herrmannsfeldt]

Sathyanarayan B wrote:

Can someone suggest me how to estimate power at RTL level?

For some reason, the previous messages that I had posted have not
appeared in this webpage.

For CMOS the power is pretty much proportional to the number
of gates changing state per unit time. For a synchronous
circuit, such as a computer, it is then proportional to clock
frequency. If you know the power used by a single gate
changing state you can get at least a rough guess from
the RTL level.

-- glen

 

[Sathyanarayan B]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<ixUvc.3785$Sw.1404@attbi_s51>...

Sathyanarayan B wrote:


Can someone suggest me how to estimate power at RTL level?

For some reason, the previous messages that I had posted have not
appeared in this webpage.

For CMOS the power is pretty much proportional to the number
of gates changing state per unit time. For a synchronous
circuit, such as a computer, it is then proportional to clock
frequency. If you know the power used by a single gate
changing state you can get at least a rough guess from
the RTL level.

-- glen

I roughly worked out the formula of - C*Vdd^2*freq. But my problem is
that in ASIC, the technology library would use different standard
cells and components and capacitance (C) for all these varies. So
given the technology library files, say TSMC 130 nm technology, how to
compute the power? Do I need to take into account all the cells of the
library or can I choose a representative set from the library and
multiply the power for that cell by a constant factor? Please clarify.

-Satya

 

[Jon Beniston]

I roughly worked out the formula of - C*Vdd^2*freq. But my problem is
that in ASIC, the technology library would use different standard
cells and components and capacitance (C) for all these varies. So
given the technology library files, say TSMC 130 nm technology, how to
compute the power? Do I need to take into account all the cells of the
library or can I choose a representative set from the library and
multiply the power for that cell by a constant factor?

It depends how accurate you want your estimate to be. The more
accurate the information you use, the closer you will be.

If you don't like Power Compiler, try this:

http://www.sequencedesign.com/2_solutions/2b_power_theater.html

Cheers,
JonB

 

[Glen Herrmannsfeldt]

Sathyanarayan B wrote:

(snip)

I roughly worked out the formula of - C*Vdd^2*freq. But my problem is
that in ASIC, the technology library would use different standard
cells and components and capacitance (C) for all these varies. So
given the technology library files, say TSMC 130 nm technology, how to
compute the power? Do I need to take into account all the cells of the
library or can I choose a representative set from the library and
multiply the power for that cell by a constant factor? Please clarify.

In the olden days (maybe 0.8 micron technology) it was possible
to model a net as a capacitor, with the capacitance reasonably
determined at the time of routing. The timing model could treat
each net as a single RC circuit. As technology evolved, it
became necessary to model as distributed resistance and capacitance,
complicating the timing and power calculations.

It is also likely that the results from routing are not as
good at predicting the capacitance, and therefor the power.
Also, you need some idea of the switching rate for each net.

-- glen