Power estimation for Synopsys Designware IP

Hi,

Sorry if this is not the most appropriate newsgroup to ask this, but I could
not find better places. Since there are so many gurus here, I still
shameless posted my question here.

I was doing some power estimation through report_power in Synopsys dc_shell
for my verilog design. It seems to me that all the power breakdown does not
make sense. More specifically, I instantiated some components (a FCFS
arbiter and a register-based FIFO) from the Synopsys DesignWare Foundation
library in my design, and found that for both these two modules, their
internal power consumption (short-circuit power) is around 3 times as large
as their dynamic switching power consumption. This is true with or without
switching factor annotation.

This does not make sense to me, as I thought usually dynamic power should be
usually dominant. (Other than the results for these two components, all the
other part makes sense).

So my question is, is there some special treatment when using IPs from DW
library?

Thanks much in advance

P.S. As an example, below is the output I got with report_power for a design
which contains only the register-based FIFO from DW without switching
activity annotation:


Global Operating Voltage = 1.8
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1uW


--------------------------------------------------------------------------------
Switch Int Leak Total
Hierarchy Power Power Power Power %
--------------------------------------------------------------------------------
DW_fifo_s1_sf_inst 2.821 7.551 7.47e-02 10.372 100.0
U1 0.457 7.551 7.47e-02 8.008 77.2