Power compiler and simulation time.

[Kelvin Tsai @ Singapore]

Hi, all:

Why does simulation clock period affect power consumption?

I am performing power analysis based on unit delay simulation on a
0.18um process. My library
uses 1ns for each cell by default. The combination logic levels are
above 5 levels while my
clock is 5 ns. so, I tried to simulate with a clock rate of 10ns
instead and get away with the
SAIF whose duration and TC0 and TC1 are all twice of what my intended,
but the ratio is good.

Now I run analysis, the power consumption halved from the number with
SAIF from zero delay simulation...

In DC I use same 5ns clock rate for both analysis. The other analysis
were performed separate with
SAIF from zero delay simulation, and was simulated at clock period of
5ns.

Is there anything wrong with my procedure? Does the

Best Regards,
Kelvin.

 

[Prasanna]

kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) wrote in message news:<bf7e7c6.0309080022.49873d7c@posting.google.com>...

Hi, all:

Why does simulation clock period affect power consumption?

I am performing power analysis based on unit delay simulation on a
0.18um process. My library
uses 1ns for each cell by default. The combination logic levels are
above 5 levels while my
clock is 5 ns. so, I tried to simulate with a clock rate of 10ns
instead and get away with the
SAIF whose duration and TC0 and TC1 are all twice of what my intended,
but the ratio is good.

Now I run analysis, the power consumption halved from the number with
SAIF from zero delay simulation...

In DC I use same 5ns clock rate for both analysis. The other analysis
were performed separate with
SAIF from zero delay simulation, and was simulated at clock period of
5ns.

Is there anything wrong with my procedure? Does the

Best Regards,
Kelvin.

Hi Kelvin,

I assume your question is regarding reporting of power for different
frequencies.

For CMOS logic, power equation is,

P = Pdyn+ Pshort + Pleak

Here dynamic power is a function of the frequency and is represented
power dissipated per Mhz.

Regards,

- Prasanna

 

[Andy]

Thank you Prasanna for your reply.

Yes the dynamic power double when the clock rates double in design compiler,
however in
my analysis, the clock rate is fixed.


Oh i guess my problem is i am only thinking of static probability and
neglected toggle rate. Anyway,
I need to tackle the RAM problem instead and stick to my zero-delay
simulation.


What is the right procedure to synthesize a design with a RAM when I don't
have a .db model for the
RAM? I only have the datasheet and .lib file generated from a RAM-Generator
supplied by the fab.


Best Regards,
Kelvin






"Prasanna" <pra_verilog@yahoo.com> wrote in message
news:feb16bd1.0309080928.6e8e6a8f@posting.google.com...

kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) wrote in message
news:<bf7e7c6.0309080022.49873d7c@posting.google.com>...
Hi, all:

Why does simulation clock period affect power consumption?

I am performing power analysis based on unit delay simulation on a
0.18um process. My library
uses 1ns for each cell by default. The combination logic levels are
above 5 levels while my
clock is 5 ns. so, I tried to simulate with a clock rate of 10ns
instead and get away with the
SAIF whose duration and TC0 and TC1 are all twice of what my intended,
but the ratio is good.

Now I run analysis, the power consumption halved from the number with
SAIF from zero delay simulation...

In DC I use same 5ns clock rate for both analysis. The other analysis
were performed separate with
SAIF from zero delay simulation, and was simulated at clock period of
5ns.

Is there anything wrong with my procedure? Does the

Best Regards,
Kelvin.

Hi Kelvin,

I assume your question is regarding reporting of power for different
frequencies.

For CMOS logic, power equation is,

P = Pdyn+ Pshort + Pleak

Here dynamic power is a function of the frequency and is represented
power dissipated per Mhz.

Regards,

- Prasanna