Power calculation using Xpower

[praveen]

hi all,

i am calculating the power consumption using xilinx xpower. For
generating the VCD file i am not loading the SDF(Standard Delay
Format) during VSIM. Will it affect the power calculation.

thanks in advance.

 

[John Blaine]

Praveen,

It is difficult to estimate how much impact this will have on the power
estimate.
So let me take you through a few points:

Using a post PAR estimate will allow XPower to have an accurate estimate
of
capacitance load on the internal routes so no problem here. If you are
using post MAP
where no SDF is generated then this is a large source of inaccuracy and
is not
recommended.

Now lets look at the timing simulations tend to result in glitches. This
switching translates
into higher activity rates in XPower-> higher power.

I would expect these to be fairly low load signals. Also if you have a
fully synchronous
design this effect will be limited.

Your clocks will be set correctly (high power consuming nets).
If you have met timing (verifed through timing analyser) then other
heavy loaded signals like
clock enables, should be set correctly.

So in summary, if your design is post PAR, fully synchronous and has met
timing, you should
be OK an get an accurate power estimate.

John

praveen wrote:

hi all,

i am calculating the power consumption using xilinx xpower. For
generating the VCD file i am not loading the SDF(Standard Delay
Format) during VSIM. Will it affect the power calculation.

thanks in advance.

 

[Austin Lesea]

All,

The power estimate is only as good as your simulation vectors, and their
length.

Short sims, few vectors = bad estimate.

Austin

John Blaine wrote:

Praveen,

It is difficult to estimate how much impact this will have on the power
estimate.
So let me take you through a few points:

Using a post PAR estimate will allow XPower to have an accurate estimate
of
capacitance load on the internal routes so no problem here. If you are
using post MAP
where no SDF is generated then this is a large source of inaccuracy and
is not
recommended.

Now lets look at the timing simulations tend to result in glitches. This
switching translates
into higher activity rates in XPower-> higher power.

I would expect these to be fairly low load signals. Also if you have a
fully synchronous
design this effect will be limited.

Your clocks will be set correctly (high power consuming nets).
If you have met timing (verifed through timing analyser) then other
heavy loaded signals like
clock enables, should be set correctly.

So in summary, if your design is post PAR, fully synchronous and has met
timing, you should
be OK an get an accurate power estimate.

John

praveen wrote:

hi all,

i am calculating the power consumption using xilinx xpower. For
generating the VCD file i am not loading the SDF(Standard Delay
Format) during VSIM. Will it affect the power calculation.

thanks in advance.

 

[praveen]

John Blaine <john.blaine@xilinx.com> wrote in message news:<3F9FA363.7930A312@xilinx.com>...

Praveen,

It is difficult to estimate how much impact this will have on the power
estimate.
So let me take you through a few points:

Using a post PAR estimate will allow XPower to have an accurate estimate
of
capacitance load on the internal routes so no problem here. If you are
using post MAP
where no SDF is generated then this is a large source of inaccuracy and
is not
recommended.

Now lets look at the timing simulations tend to result in glitches. This
switching translates
into higher activity rates in XPower-> higher power.

I would expect these to be fairly low load signals. Also if you have a
fully synchronous
design this effect will be limited.

Your clocks will be set correctly (high power consuming nets).
If you have met timing (verifed through timing analyser) then other
heavy loaded signals like
clock enables, should be set correctly.

So in summary, if your design is post PAR, fully synchronous and has met
timing, you should
be OK an get an accurate power estimate.

John

praveen wrote:

hi all,

i am calculating the power consumption using xilinx xpower. For
generating the VCD file i am not loading the SDF(Standard Delay
Format) during VSIM. Will it affect the power calculation.

thanks in advance.

--

hi john,

as u said our design is fully synchronous and our entire design is
working on only one clock edge, and more over ther are no latches
inferred in our design , so chances of glitches are minimal.

so not loading the SDF file will not make much differnce in th power
estimate i guess.

one more thing i wanted to ask u regarding the power consumption, we r
using XILINX virtex 2p (XC2VP50 -6 FF1517) . what is the power that is
tolerable without providing heat sinks.

praveen

 

[Brendan Cullen]

Hi Praveen,

Are you asking what power, given room temperature operation, would send the junction temperature
to over 85 degrees Celsius ?

Brendan

praveen wrote:

John Blaine <john.blaine@xilinx.com> wrote in message news:<3F9FA363.7930A312@xilinx.com>...
Praveen,

It is difficult to estimate how much impact this will have on the power
estimate.
So let me take you through a few points:

Using a post PAR estimate will allow XPower to have an accurate estimate
of
capacitance load on the internal routes so no problem here. If you are
using post MAP
where no SDF is generated then this is a large source of inaccuracy and
is not
recommended.

Now lets look at the timing simulations tend to result in glitches. This
switching translates
into higher activity rates in XPower-> higher power.

I would expect these to be fairly low load signals. Also if you have a
fully synchronous
design this effect will be limited.

Your clocks will be set correctly (high power consuming nets).
If you have met timing (verifed through timing analyser) then other
heavy loaded signals like
clock enables, should be set correctly.

So in summary, if your design is post PAR, fully synchronous and has met
timing, you should
be OK an get an accurate power estimate.

John

praveen wrote:

hi all,

i am calculating the power consumption using xilinx xpower. For
generating the VCD file i am not loading the SDF(Standard Delay
Format) during VSIM. Will it affect the power calculation.

thanks in advance.

--

hi john,

as u said our design is fully synchronous and our entire design is
working on only one clock edge, and more over ther are no latches
inferred in our design , so chances of glitches are minimal.

so not loading the SDF file will not make much differnce in th power
estimate i guess.

one more thing i wanted to ask u regarding the power consumption, we r
using XILINX virtex 2p (XC2VP50 -6 FF1517) . what is the power that is
tolerable without providing heat sinks.

praveen

 

[Brendan Cullen]

Hi Praveen,

Brendan Cullen wrote:

Hi Praveen,

Are you asking what power, given room temperature operation, would send the junction temperature
to over 85 degrees Celsius ?

Brendan

praveen wrote:

John Blaine <john.blaine@xilinx.com> wrote in message news:<3F9FA363.7930A312@xilinx.com>...
Praveen,

It is difficult to estimate how much impact this will have on the power
estimate.
So let me take you through a few points:

Using a post PAR estimate will allow XPower to have an accurate estimate
of
capacitance load on the internal routes so no problem here. If you are
using post MAP
where no SDF is generated then this is a large source of inaccuracy and
is not
recommended.

Now lets look at the timing simulations tend to result in glitches. This
switching translates
into higher activity rates in XPower-> higher power.

I would expect these to be fairly low load signals. Also if you have a
fully synchronous
design this effect will be limited.

Your clocks will be set correctly (high power consuming nets).
If you have met timing (verifed through timing analyser) then other
heavy loaded signals like
clock enables, should be set correctly.

So in summary, if your design is post PAR, fully synchronous and has met
timing, you should
be OK an get an accurate power estimate.

John

praveen wrote:

hi all,

i am calculating the power consumption using xilinx xpower. For
generating the VCD file i am not loading the SDF(Standard Delay
Format) during VSIM. Will it affect the power calculation.

thanks in advance.

--

hi john,

as u said our design is fully synchronous and our entire design is
working on only one clock edge, and more over ther are no latches
inferred in our design , so chances of glitches are minimal.

Having a synchronous design does not mean that a node will change only once per clock cycle. All it
means is that all nodes need to be stable before the next clock cycle. In other words, the nodes in
between two registers in a fully synchronous data path may change from 1 to 0 and back to 1 again
several times within a clock cycle and that is OK as long as it is stable before the next clock
cycle arrives. The reason it may oscillate like that is the inputs to the logic functions will
arrive
at different times depending on the component and routing delays and depending on the logic
functions and the input values any node may change several times in between clock cycles. The
reason this is important to know is the way to calculate dynamic power depends on how often each
node changes value (Dynamic Power = Capacitance * Voltage^2 Frequency the node changes). If you do
a non-timing simulation and do not account for delays in the design, these "glitches" for lack of a
better word will not be simulated and thus not given to XPower and thus will not get as accurate of
an estimation for power since the frequency
part of the equation will not be accurate.

There is even more to it than that. Within the SDF file are parameters called PATHPULSE which
define which glitches get propogated and which ones will get absorbed by the capacitance within the
chip. This will get rid of some glitches that will likely not get realized in the silicon simply
because they are too short to overcome the node capacitance. Without an SDF file, it is possible
that some transitions within the non-timing simulation would not happen and for timing simulation,
some of the "glithes" will happen and some will not. This parameter is the one that gates that
behavior and thus can effect the number of tranitions at a node and thus the dynamic power at that
node.

so not loading the SDF file will not make much differnce in th power
estimate i guess.

It very likely can. I would highly recommend doing power estimations with SDF only as it is much
more likely to accurately predict power than not using one.

one more thing i wanted to ask u regarding the power consumption, we r
using XILINX virtex 2p (XC2VP50 -6 FF1517) . what is the power that is
tolerable without providing heat sinks.

As long as the junction temperature is below 85 degrees for comercial devices, then you are OK. The
junction temperature is dependent on the amount of power dissipated as well as the ambient
temperature, airflow, and heat dissipation of the device (through the package, heatsink, and the
board itself). Once it gets above that, you need to cool the device and a heatsink is one way to do
that.

XPower allows you to enter information like ambient temperature and airflow so that it can calculate
the junction temperature based on those parameters as well as the power dissipated. As long as that
is below 85 degrees (with some margin) then you should be OK without a heatsink. If not, you need
to either look into a heatsink or possibly change other environmental factors to get the device
within specification.

Brendan