POST SYNTHESYS SIMULATION

[ec]

Hi all
Is it posible to simulate after plac and route ?
what I mean is it possible to see the delays contributed to the model after
place and route in the vhdl code?

Thanks
EC

 

[KJ]

ec wrote:

Hi all
Is it posible to simulate after plac and route ?
what I mean is it possible to see the delays contributed to the model after
place and route in the vhdl code?

Thanks
EC

Yes, one of the outputs of place and route is a VHDL (or Verilog)
simulation model that incorporates expected propogation delays.

Although the time delays are in the model, this model does not become a
substitute for performing timing analysis since the model does not
allow you to use the full range of delays under all conditions (i.e.
you can do 'min', 'max' or 'typical' timing but no mix and match) so
simulation with this model is generally of limited utility...plus it
will run much slower than the functional model that was the input to
synthesis.

KJ

 

[Hubble]

"Simulate all possible stages in all combinations" is not possible in any
but the most trivial design (like anything above a CPLD) in any time frame
that is less than that required to perform static timing analysis. Not to
mention even being able to define what 'all combinations' really means
(hint: it's not getting 100% line code coverage, but getting 100% line code
coverage under all possible combinations of input and states).

Hint: I mentioned medium sized designs. You can give an upper limit of
all combinations in combinatorial and RTL designs (the most common ones
for synthesis), which is simply 2^(inputs+internal signals). Too big
for all designs above ~60 signals.

Hubble.

 

[Hubble]

KJ schrieb:

ec wrote:
Hi all
Is it posible to simulate after plac and route ?
what I mean is it possible to see the delays contributed to the model after
place and route in the vhdl code?

Yes, one of the outputs of place and route is a VHDL (or Verilog)
simulation model that incorporates expected propogation delays.

Which usually consists of the netlist in e.g. VHDL which comes from the

synthesis stage and an SDF (standard delay format) file which is in
EDIF file and contains min/typ/max timings for each instance. Using a
simulator like Modelsim, you can do the following:

- compile the (VHDL) netlist
- In your testbench, create a new architecture for the top entity of
the design (which is part of the testbench)
- Start modelsim. Instruct it to use the SDF file for the design and
max timing
- Run your tests
- Redo it with min.

Min/Max are sufficient if you simulate all possible stages in all
combinations. Since this is not possible for medium sized and big sized
designs, an additional static time analysis is required for ASICs.

Hubble.

 

[KJ]

"Hubble" <reiner@huober.de> wrote in message
news:1162444520.241922.14670@m73g2000cwd.googlegroups.com...

KJ schrieb:


Min/Max are sufficient if you simulate all possible stages in all
combinations. Since this is not possible for medium sized and big sized
designs, an additional static time analysis is required for ASICs.

"Simulate all possible stages in all combinations" is not possible in any

but the most trivial design (like anything above a CPLD) in any time frame
that is less than that required to perform static timing analysis. Not to
mention even being able to define what 'all combinations' really means
(hint: it's not getting 100% line code coverage, but getting 100% line code
coverage under all possible combinations of input and states).

KJ