Post Synthesis, Post PAR, and real hardware behavior?

Hi all,

I just started in VHDL. I wrote the code and performed a functional
simulation (pre-synthesis). Output is what I expected. Performed a
post synthesis simulation, obtained similar results. Then the post
place-and-route (PAR) simulation gave me 'X' (don't care?) as part of
the output.

I then programed the device and the output is what I saw in the
functional and post synthesis simulation results.

My question is, what's the difference between these simulation models
(post synthesis and post PAR)? Given that the post PAR simulation
model is closest to hardware, how come the result is different from
the actual output?

Thanks in advance!

 

[Mike Treseler]

scott.yuan523@gmail.com wrote:

My question is, what's the difference between these simulation models
(post synthesis and post PAR)? Given that the post PAR simulation
model is closest to hardware, how come the result is different from
the actual output?

This is most likely a bug in the testbench
reset/clock synchronization, not the synthesis code.
If you pass static timing and it
works on the bench, I wouldn't
spend much time on it.

-- Mike Treseler

 

[Thomas Stanka]

On 25 Apr., 19:03, scott.yuan...@gmail.com wrote:

I just started in VHDL. I wrote the code and performed a functional
simulation (pre-synthesis). Output is what I expected. Performed a
post synthesis simulation, obtained similar results. Then the post
place-and-route (PAR) simulation gave me 'X' (don't care?) as part of
the output.

Don't care is '-', 'X' means unknown. A X can be obtained by two
driver on the same signal, but also if there is no driver for a signal
or if your library throws 'X' after setup/hold violations.
A 'X' is not necessarily an error, but something you need to inspect
carefully.

bye Thomas

 

Thanks for the responses!

On Apr 26, 4:11 am, Thomas Stanka <usenet...@stanka-web.de> wrote:

Don't care is '-', 'X' means unknown. A X can be obtained by two
driver on the same signal, but also if there is no driver for a signal
or if your library throws 'X' after setup/hold violations.
A 'X' is not necessarily an error, but something you need to inspect
carefully.

bye Thomas

I looked at both the RTL and technology schematic. There's only one
driver for the output.

 

[Andy]

On Apr 26, 3:11 am, Thomas Stanka <usenet...@stanka-web.de> wrote:

On 25 Apr., 19:03, scott.yuan...@gmail.com wrote:

I just started in VHDL. I wrote the code and performed a functional
simulation (pre-synthesis). Output is what I expected. Performed a
post synthesis simulation, obtained similar results. Then the post
place-and-route (PAR) simulation gave me 'X' (don't care?) as part of
the output.

Don't care is '-', 'X' means unknown. A X can be obtained by two
driver on the same signal, but also if there is no driver for a signal
or if your library throws 'X' after setup/hold violations.
A 'X' is not necessarily an error, but something you need to inspect
carefully.

bye Thomas

Typically the result of no driver for a std_logic signal is a
'U' (uninitialized), rather than an 'X', unless there is an explicit
initializer in the signal declaration.

Andy

 

[Thomas Stanka]

On 26 Apr., 19:37, Andy <jonesa...@comcast.net> wrote:

Don't care is '-', 'X' means unknown. A X can be obtained by two
driver on the same signal, but also if there is no driver for a signal
or if your library throws 'X' after setup/hold violations.
A 'X' is not necessarily an error, but something you need to inspect
carefully.

Typically the result of no driver for a std_logic signal is a
'U' (uninitialized), rather than an 'X', unless there is an explicit
initializer in the signal declaration.

You are right, I was a bit fast. A signal with no driver is a U in
first place. I thought about GTL-gates driving X when having no driver
(U at an Input). I see this sometimes especially when using Verilog
library elements.

bye Thomas