Post Synthesis and Post Place/Rout Simulation

For: Aldec Riviera-PRO 2007.10 and Active_HDL 7.2.

Does anyone have an example simulation .do file for Post Synthesis and
Post Place/Rout Simulation.

Question is "How to correctly point to gate-level sim files"?

Thanks.

 

[Mike Treseler]

wjrousey@wildblue.net wrote:

Question is "How to correctly point to gate-level sim files"?

After the functional testbench sims ok (step 1)
compile the gate module over the rtl using the
same name, and sim again. If everything
lines up ok, expect the same answer,
but it will take longer.


-- Mike Treseler