M
Mehmood
Guest
I am using ModelSim 5.4d and Xilinx ISE 5.2 . I have entered all my
designed and have completed all the step to "GENERATE PROGRAMMING
FILE". I am able to get functional simulation. Then for post-translate
verilog model, i created a simprim in my project root directory.
However, when i load the file, i need *.sdf file. I thought that it
should be created by Xilinx ISE when i synthesis the project. However,
i am not able to find any *.sdf file any where.
First question is am i doing everything correctly. (i mean build
simprim)?
Second question is where is the sdf file of my project?
Is there any automatic way of doing this synthesis without manually
building simprim and then load design?
I do not know which step is wrong.
Anyone any ideas?
Regards,
Mehmood
designed and have completed all the step to "GENERATE PROGRAMMING
FILE". I am able to get functional simulation. Then for post-translate
verilog model, i created a simprim in my project root directory.
However, when i load the file, i need *.sdf file. I thought that it
should be created by Xilinx ISE when i synthesis the project. However,
i am not able to find any *.sdf file any where.
First question is am i doing everything correctly. (i mean build
simprim)?
Second question is where is the sdf file of my project?
Is there any automatic way of doing this synthesis without manually
building simprim and then load design?
I do not know which step is wrong.
Anyone any ideas?
Regards,
Mehmood