Post-Map Simulation

K

Kavitha

Guest
Hi!
I am new to this news group.I am doing my project work in Xilinx(ISE
5.2).I use Modelsim 5.6e for simulations. My design is in VHDL. The
simulations for Behavioral and Post-Translate are coming as
expected.But Modelsim is showing error when I do Post-Map simulations.
Name of my entity is strem_entity and testbench is test_bench.

----------------------------------------------------
Modelsim is giving the following error:
----------------------------------------------------
# ** Error: (vsim-SDF-3250) stream_entity_map.sdf(0): Failed to find
INSTANCE '/UUT'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test_bench.mdo PAUSED at line 10.
-------------------------------------------------------

When I open and see test_bench.mdo in note pad,it has following
contents:
-------------------------------------------------------------------------
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Map Simulation
##
vlib work
## Compile Post-Map Model for Module streamcompression
vcom -just e -87 -explicit -work work stream_entity_map.vhd
vcom -skip e -87 -explicit -work work stream_entity_map.vhd
vcom -just e -93 -explicit -work work test_bench.vhd
vcom -skip e -93 -explicit -work work test_bench.vhd
vsim -t 1ps -sdfmax /UUT=stream_entity_map.sdf -lib work testbench
do test_bench.udo
view wave
add wave *
view structure
view signals
view process
run 0ps
## End
--------------------------------------------------------------

I don't have a instance by name UUT in my design.I think that is
created by project navigator.Could any one help me regarding this.I am
not able to understan why is modelsim giving the message.It would you
be great if any one can help me to over come this problem.

Thank you,
-Kavi
 
Hi,
In ISE, in the properties of "Simulate Post-Place..." , you have to change
the value of "UUT instance name" (which defaults to UUT), to the name you
have used in your testbench to instantiate the design you are testing.

Arnaud

"Kavitha" <fpga_group_04@yahoo.com> a écrit dans le message de
news:3bcfe252.0406251255.1cbf4ad6@posting.google.com...
Hi!
I am new to this news group.I am doing my project work in Xilinx(ISE
5.2).I use Modelsim 5.6e for simulations. My design is in VHDL. The
simulations for Behavioral and Post-Translate are coming as
expected.But Modelsim is showing error when I do Post-Map simulations.
Name of my entity is strem_entity and testbench is test_bench.

----------------------------------------------------
Modelsim is giving the following error:
----------------------------------------------------
# ** Error: (vsim-SDF-3250) stream_entity_map.sdf(0): Failed to find
INSTANCE '/UUT'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test_bench.mdo PAUSED at line 10.
-------------------------------------------------------

When I open and see test_bench.mdo in note pad,it has following
contents:
-------------------------------------------------------------------------
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Map Simulation
##
vlib work
## Compile Post-Map Model for Module streamcompression
vcom -just e -87 -explicit -work work stream_entity_map.vhd
vcom -skip e -87 -explicit -work work stream_entity_map.vhd
vcom -just e -93 -explicit -work work test_bench.vhd
vcom -skip e -93 -explicit -work work test_bench.vhd
vsim -t 1ps -sdfmax /UUT=stream_entity_map.sdf -lib work testbench
do test_bench.udo
view wave
add wave *
view structure
view signals
view process
run 0ps
## End
--------------------------------------------------------------

I don't have a instance by name UUT in my design.I think that is
created by project navigator.Could any one help me regarding this.I am
not able to understan why is modelsim giving the message.It would you
be great if any one can help me to over come this problem.

Thank you,
-Kavi
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top