Possible to produce Minus 5 v ???

[Sridhar_Gadda]

hello Friends

it is possible to produce -1 at the output port. I have written a simple
code.

reg d;
initial
d = -1;

always at (posedge clock)
q = d;

After simulation, I got the value of q as 1. I souppose to get -1. It is
not possible to produce negative voltages in verilog ?? Only we have to
work with 1's and 0's ??

Thanks in advance

Sridhar

 

[Jason Zheng]

Sridhar_Gadda wrote:

hello Friends

it is possible to produce -1 at the output port. I have written a simple
code.

reg d;
initial
d = -1;

always at (posedge clock)
q = d;

After simulation, I got the value of q as 1. I souppose to get -1. It is
not possible to produce negative voltages in verilog ?? Only we have to
work with 1's and 0's ??

Thanks in advance

Sridhar

There are only 0's and 1's in digital design, and the reason why you are

seeing 1 on the output is that the two's compliment of -1 is 32'hffff,
which is the value that your verilog compiler translates to. To get -1,
you might want to add an inverting ANALOG op-amp circuitry on that
output pin. A quick google search on op-amp tutorial will show you how
to implement that.

-jz

 

[Mike Lewis]

"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message
news:dfa8c2abfc4fc7c1b7e2133e6cd34ea7@localhost.talkaboutprogramming.com...

hello Friends

it is possible to produce -1 at the output port. I have written a simple
code.

reg d;
initial
d = -1;

always at (posedge clock)
q = d;

After simulation, I got the value of q as 1. I souppose to get -1. It is
not possible to produce negative voltages in verilog ?? Only we have to
work with 1's and 0's ??

Thanks in advance

Sridhar

Well the quick answer is no ... verilog doesn't produce any specific
voltage. It produces a "logic high/low" that is applied to your technology
that
produces the actual voltages (TTL, LVTTL, SSTTL, etc).

 

[DW]

"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message
news:dfa8c2abfc4fc7c1b7e2133e6cd34ea7@localhost.talkaboutprogramming.com...

hello Friends

it is possible to produce -1 at the output port. I have written a simple
code.

reg d;
initial
d = -1;

always at (posedge clock)
q = d;

After simulation, I got the value of q as 1. I souppose to get -1. It is
not possible to produce negative voltages in verilog ?? Only we have to
work with 1's and 0's ??

Thanks in advance

Sridhar

d is only 1 bit wide and therefore cannot really carry any signed values.

If you had a 2 bit port i.e.
output signed [1:0] q;
then q could take on values -2, -1, 0, +1. You would have to ensure that
your simulator viewed q as a signed decimal number - it may well interpret
it as unsigned (decimal, hex, octal or binary etc) unless you tell it
otherwise.

I think you are confusing things by talking about voltages in the same
sentence as Verilog. To produce a voltage, you would have to take some
digtial information and convert it to analogue with appropriate scaling for
your system.