Possibility to use MGTREFCLK1P/MGTREFCLK1N as clock for user

Hi,

Due to broken design of the FPGA board, I have the master clock available only at MGTREFCLK1P/MGTREFCLK1N pins.
Is it possible to use those pins to produce clock for use logic in FPGA instead of GTP transceiver?

If I try to connect those pins to the differential input buffer, I get the following errors:

Mapping design into LUTs...
Running directed packing...
ERRORack:1107 - Pack was unable to combine the symbols listed below into a
single IOB component because the site type selected is not compatible.

Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
IOB was chosen because the IO contains symbols and/or properties consistent
with input, output, or bi-directional usage and contains no other symbols or
properties that require a more specific IO component type. Please double
check that the types of logic elements and all of their relevant properties
and configuration options are compatible with the physical site type of the
constraint.

Summary:
Symbols involved:
PAD symbol "gtc_n5" (Pad Signal = gtc_n5)
SlaveBuffer symbol "ib1/SLAVEBUF.DIFFIN" (Output Signal =
ib1/SLAVEBUF.DIFFIN)
Component type involved: IOB
Site Location involved: AK19
Site Type involved: IPAD

ERRORack:1107 - Pack was unable to combine the symbols listed below into a
single IOB component because the site type selected is not compatible.

Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
IOB was chosen because the IO contains symbols and/or properties consistent
with input, output, or bi-directional usage and contains no other symbols or
properties that require a more specific IO component type. Please double
check that the types of logic elements and all of their relevant properties
and configuration options are compatible with the physical site type of the
constraint.

Summary:
Symbols involved:
PAD symbol "gtc_p5" (Pad Signal = gtc_p5)
DIFFAMP symbol "ib1/IBUFDS" (Output Signal = io_clk)
Component type involved: IOB
Site Location involved: AJ19
Site Type involved: IPAD

Is there any component (BUFIO2, or something similar) able to produce normal clock from those pins?
--
TIA & Regards,
WZab

 

[Mark Curry]

In article <af2d18b0-beec-47ac-afd9-49c024034fdd@googlegroups.com>,
<wzab01@gmail.com> wrote:

Hi,

Due to broken design of the FPGA board, I have the master clock available only at MGTREFCLK1P/MGTREFCLK1N pins.
Is it possible to use those pins to produce clock for use logic in FPGA instead of GTP transceiver?

If I try to connect those pins to the differential input buffer, I get the following errors:

snip error log

Is there any component (BUFIO2, or something similar) able to produce normal clock from those pins?

I think the clock must still go through the GTPA1_DUAL. Then use the output pin "GTPCLKOUT[0|1]", connect
that to a BUFIO2, then connect the output of the BUFIO2 to a BUFG.

I know we've done similar with a virtex6 GTX, and we put the above hooks in place
for the Spartan6 versions of our boards. I just don't know if we tested it.

It's a good place to start. In any case I'm fairly sure you have to go through the
GTP in some form - you can't just tap the clocks directly.

In any event, pour over the clocking section of the GTP user's guide. It should give you what
you need.

Regards,

Mark