posedge

[Amir]

Hi,
when I do something like:

always @( posedge ceb )
begin
....
end

do I get to this always also when the 'ceb' signal gets from 'x' to
'1'?

Thanks
-Amir

 

[Jonathan Bromley]

On Wed, 10 Sep 2008 01:36:45 -0700 (PDT), Amir <sting.t2@gmail.com>
wrote:

Hi,
when I do something like:

always @( posedge ceb )
[...]
do I get to this always also when the 'ceb' signal gets from 'x' to
'1'?

Yes. posedge accepts anything in a vaguely upwards direction:
0->x, x->1, 0->z, z->1. Make sure your clock signals are clean

Is "ceb" really a clock? Do you want to detect its rising edge?
Its name sounds like a clock enable to me...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Amir]

On Sep 10, 12:26 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Wed, 10 Sep 2008 01:36:45 -0700 (PDT), Amir <sting...@gmail.com
wrote:



Hi,
when I do something like:

always @( posedge ceb )
[...]
do I get to this always also when the 'ceb' signal gets from 'x' to
'1'?

Yes.  posedge accepts anything in a vaguely upwards direction:
0->x, x->1, 0->z, z->1.  Make sure your clock signals are clean

Is "ceb" really a clock? Do you want to detect its rising edge?
Its name sounds like a clock enable to me...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks,
Actually it's Chip Enable, is there any way to make the posedge only
like 0->1?
since the problem I'm facing is that I get into the always when the
signal is x/z and it's pulled-up .
I only need to get this always block only when I have 0->1
is this possible?

Thanks
-Amir

 

[Mark McDougall]

Amir wrote:

Actually it's Chip Enable, is there any way to make the posedge only
like 0->1?
since the problem I'm facing is that I get into the always when the
signal is x/z and it's pulled-up .
I only need to get this always block only when I have 0->1
is this possible?

Why do you have X's feeding into your clock-enable? Sounds more like you
need to sort your simulation start-up conditions?

And why do you have a pull-up on an (I'm assuming) active-high
chip-enable? Regardless, a 'Z' with a pullup should give desired results...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266