@(posedge clk)

[vittal]

Hi,
What does a statement like @(posedge clk) synthesise to?
if i write:-

input b;
output c;
a=b;
@(posedge clk);
c=a;

 

[Ben Jackson]

On 2006-12-11, vittal <vittal.patil@gmail.com> wrote:

Hi,
What does a statement like @(posedge clk) synthesise to?
if i write:-

input b;
output c;
a=b;
@(posedge clk);
c=a;

Verilog introductions are TERRIBLE about clarifying what's synthesizable
and what's not. Verilog is two languages in one -- one procedural
language that is useful for controlling simulations, and one hardware
description language which can be synthesized. Your sequence of
instructions might be useful for an input stimulus file, but not for
describing hardware.

--
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

 

[Neo]

vittal wrote:

Hi,
What does a statement like @(posedge clk) synthesise to?
if i write:-

input b;
output c;
a=b;
@(posedge clk);
c=a;

Assuming your 'a' is a reg it will systhesize to one DFF with input b
and ouput c.

 

[vits]

ok I will put it like this..
always @(*)
begin
a=b;
@(posedge clk);
c=a;
end
What does it mean.
Neo wrote:

vittal wrote:
Hi,
What does a statement like @(posedge clk) synthesise to?
if i write:-

input b;
output c;
a=b;
@(posedge clk);
c=a;

Assuming your 'a' is a reg it will systhesize to one DFF with input b
and ouput c.

 

[mjl296@hotmail.com]

vits wrote:

ok I will put it like this..
always @(*)
begin
a=b;
@(posedge clk);
c=a;
end
What does it mean.

It is a bad idea. Synthesis tools will reject this code, and although a
simulator will process it, nobody reading your code will be able to
understand or maintain it.

To help you understand it, I'll explain what it does in simulation...

1) It waits for an event on a, b or clk
2) It sets a=b
3) It waits for a rising clock edge
4) It sets c=a
5) It loops from step 1.

Neo wrote:
vittal wrote:
Hi,
What does a statement like @(posedge clk) synthesise to?
if i write:-

input b;
output c;
a=b;
@(posedge clk);
c=a;

Assuming your 'a' is a reg it will systhesize to one DFF with input b
and ouput c.

 

[Andreas Ehliar]

On 2006-12-11, mjl296@hotmail.com <mjl296@hotmail.com> wrote:

vits wrote:

ok I will put it like this..
always @(*)
begin
a=b;
@(posedge clk);
c=a;
end
What does it mean.

It is a bad idea. Synthesis tools will reject this code, and although a
simulator will process it, nobody reading your code will be able to
understand or maintain it.

To help you understand it, I'll explain what it does in simulation...

1) It waits for an event on a, b or clk
2) It sets a=b
3) It waits for a rising clock edge
4) It sets c=a
5) It loops from step 1.

I thought this was an intriguing question because I did not know how
@(*) deals with clk in the case above so I looked it up in
the Verilog standard. (IEEE Std 1364-2005 to be exact, section
9.7.5.)

It turns out that @(*) should add all (net and variable) identifiers to
the sensitivity list unless at least one of the following is true:
* It is only used as a destination for an assignment
* It only appears in a wait or event expression.

The following is an example from the standard:
always @* begin // equivalent to a(b)
@(i) kid = b; // i is not added to @*
end


So the example above should be modified as follows:

1) It waits for an event on a or b


I could also note that the version of Modelsim I'm using (6.2b) does seem
to add identifiers in event expressions to the sensitivity list
unfortunately.

/Andreas