@(posedge clk) clk[=2] |->

[--Ross]

Looking to skip first two system clocks before checking that my
next_state bus has only one bit set low

x1 : assert property ( @(posedge clk) clk[=2] |-> $onehot( !
next_state ) );

above didn't do it
--Ross

 

[Jonathan Bromley]

On Fri, 6 Jun 2008 12:02:07 -0700 (PDT), --Ross
<rossandbeth@gmail.com> wrote:

Looking to skip first two system clocks before checking that my
next_state bus has only one bit set low

x1 : assert property ( @(posedge clk) clk[=2] |-> $onehot( !
next_state ) );

You can never test a clock in an assertion; the sampled value
of the clock is sure to be its value as it was just before
the clock edge.

Try this instead...

assert property (@(posedge clk) 1[*2] |=> $onehot(...) );

The left-hand side will be satisfied on clock number 2, 3, 4...
and so on all the way through the sim.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[kookoo4systemverilog]

"--Ross" <rossandbeth@gmail.com> wrote in message
news:7a978487-3a0a-4dde-8165-3e0f118f0861@g16g2000pri.googlegroups.com...

Looking to skip first two system clocks before checking that my
next_state bus has only one bit set low

x1 : assert property ( @(posedge clk) clk[=2] |-> $onehot( !
next_state ) );

?!?
$onehot( !next_state )

Surely, you want the () expression to evaluate as a VECTOR and not a
single-bit?
Don't you mean $onehot( ~next_state ) ?