posedge and vectors

M

mm77

Guest
Hi all!
I'm a bit new to Verilog-AMS.
I need to model a comparator.
Several analog input signals are sampled when some digital signals
change state.
I thought I could use something like (next is not the actual code,
just simplified version to show my point):

----------------------

`include "constants.vams"
`include "disciplines.vams"

module Comp (Ph, PhB, v0, v1, vo);
input [2:0] Ph, PhB;
input v0, v1;
output vo;

electrical v0, v1;
logic [2:0] Ph;
logic [2:0] PhB;
electrical vo;

parameter real gain = 10000;
parameter real offset = 0;
parameter real delay = 160n;

// sampled differential input signal
real v0_val;
// differential ramp signal
real v1_val;
// output signal
real vo_val;

analog begin

// sample the signal
@ (posedge Ph[0]) begin
v0_val = V(v0) ;
end

// sample the signal
@ (negedge Ph[1]) begin
v1_val = V(v1) ;
end

if (Ph[3])
vo_val = 0;
else begin
vo_val = 1.65 - gain*(v0 - v1 - offset);
end

V(vo) <+ absdelay (vo_val, delay);

end

endmodule


-----

Apparently this doesn't work (but compiles and elaborates, just
doesn't do what expected).
Why?

Note that it works if I use separate signals (Ph2, Ph1, Ph0).
However I want to group them in a vector since they are in the
schematic I am modeling.
I haven't found any example showing this usage (posedge on vector)....
Is it not supported in Verilog-AMS? Why Not?

Thanks for any hint/help/information!
Kind regards,

Marco
 
On Mon, 31 May 2010 09:41:47 -0700 (PDT), mm77 wrote:

I'm a bit new to Verilog-AMS.
I need to model a comparator.
Several analog input signals are sampled when some digital signals
change state.
I thought I could use something like (next is not the actual code,
just simplified version to show my point):

----------------------

`include "constants.vams"
`include "disciplines.vams"

module Comp (Ph, PhB, v0, v1, vo);
input [2:0] Ph, PhB;
input v0, v1;
output vo;

electrical v0, v1;
logic [2:0] Ph;
logic [2:0] PhB;
electrical vo;
[...]
analog begin

// sample the signal
@ (posedge Ph[0]) begin
v0_val = V(v0) ;
end
Click to expand...
This would certainly be fine in digital Verilog. Any
single bit of a vector is just a bit, and can take part
in (posedge) and other operations in the way you
would expect.

There are some tricky areas if you try to do posedge on
a whole vector: are you looking for any increase in
value? A posedge on (|vec) ? Actually the standard
says that [pos|neg]edge tests only the least significant
bit of the vector. But that's not what you are
doing; you're testing an individual bit of a vector,
and that should be fine.

Note that it works if I use separate signals (Ph2, Ph1, Ph0).
Click to expand...
Weird. You need a friendly AMS guru, and that ain't me.

Good luck
--
Jonathan Bromley
 
mm77 wrote:
Hi all!
I'm a bit new to Verilog-AMS.
I need to model a comparator.
Several analog input signals are sampled when some digital signals
change state.
I thought I could use something like (next is not the actual code,
just simplified version to show my point):

----------------------

`include "constants.vams"
`include "disciplines.vams"

module Comp (Ph, PhB, v0, v1, vo);
input [2:0] Ph, PhB;
input v0, v1;
output vo;

electrical v0, v1;
logic [2:0] Ph;
logic [2:0] PhB;
electrical vo;

parameter real gain = 10000;
parameter real offset = 0;
parameter real delay = 160n;

// sampled differential input signal
real v0_val;
// differential ramp signal
real v1_val;
// output signal
real vo_val;

analog begin

// sample the signal
@ (posedge Ph[0]) begin
v0_val = V(v0) ;
end

// sample the signal
@ (negedge Ph[1]) begin
v1_val = V(v1) ;
end

if (Ph[3])
vo_val = 0;
else begin
vo_val = 1.65 - gain*(v0 - v1 - offset);
end

V(vo) <+ absdelay (vo_val, delay);

end

endmodule
Click to expand...
As a minimum I'm assuming this should be PH[2] in the "if" condition and
v0 and v1 should be v0_val and v1_val in the vo_val calculation. After
that I'd need more information. You could use $strobe to verify that the
values are being updated when/as you expect. I don't normally use AMS.
It's either straight Verilog-A or Verilog-D for me. I'm assuming you
don't need to deal with interface elements. As a workaround you may be
able to create a digital continuous assignment (outside the analog
block) that splits the bits into individual bits that are used in the
analog block. That would also give them nice descriptive names.

You may also want to check out the forums on "The Designer's Guide"
website. They specialize in AMS discussions.

Cary
 
On Jun 1, 2:01 am, "Cary R." <no-s...@host.spam> wrote:
mm77 wrote:
Hi all!
I'm a bit new to Verilog-AMS.
I need to model a comparator.
Several analog input signals are sampled when some digital signals
change state.
I thought I could use something like (next is not the actual code,
just simplified version to show my point):

----------------------

`include "constants.vams"
`include "disciplines.vams"

module Comp (Ph, PhB, v0, v1, vo);
input [2:0] Ph, PhB;
input v0, v1;
output vo;

electrical v0, v1;
logic [2:0] Ph;
logic [2:0] PhB;
electrical vo;

parameter real gain = 10000;
parameter real offset = 0;
parameter real delay = 160n;

    // sampled differential input signal
    real v0_val;
    // differential ramp signal
    real v1_val;
    // output signal
    real vo_val;

    analog begin

        // sample the signal
        @ (posedge Ph[0]) begin
            v0_val = V(v0) ;
        end

        // sample the signal
        @ (negedge Ph[1]) begin
            v1_val = V(v1) ;
        end

        if (Ph[3])
            vo_val = 0;
        else begin
            vo_val = 1.65 - gain*(v0 - v1 - offset);
        end

        V(vo) <+ absdelay (vo_val, delay);

    end

endmodule

As a minimum I'm assuming this should be PH[2] in the "if" condition and
v0 and v1 should be v0_val and v1_val in the vo_val calculation. After
that I'd need more information. You could use $strobe to verify that the
values are being updated when/as you expect. I don't normally use AMS.
It's either straight Verilog-A or Verilog-D for me. I'm assuming you
don't need to deal with interface elements. As a workaround you may be
able to create a digital continuous assignment (outside the analog
block) that splits the bits into individual bits that are used in the
analog block. That would also give them nice descriptive names.

You may also want to check out the forums on "The Designer's Guide"
website. They specialize in AMS discussions.

Cary
Click to expand...
Hi Cary,

yes, you are right about Ph[2] and v0_val and v1_val (I just typed in
here that code instead of the actual one).

I tried to create and assignment from, e.g., Ph[2] to Ph2:



---------------
logic PhE;

always begin
PhE = Ph[2];
end

analog begin

@(posedege(PhE) begin
...


-----------------------
But I got an error at the assignment line:
"a net is not a legal lvalue in this context".
I tried also putting that assignment (without the always) inside the
analog block, but I got the same message.

Cheers,
Marco
 
mm77 wrote:
On Jun 1, 2:01 am, "Cary R." <no-s...@host.spam> wrote:
mm77 wrote:
Hi all!
I'm a bit new to Verilog-AMS.
I need to model a comparator.
Several analog input signals are sampled when some digital signals
change state.
I thought I could use something like (next is not the actual code,
just simplified version to show my point):
----------------------
`include "constants.vams"
`include "disciplines.vams"
module Comp (Ph, PhB, v0, v1, vo);
input [2:0] Ph, PhB;
input v0, v1;
output vo;
electrical v0, v1;
logic [2:0] Ph;
logic [2:0] PhB;
electrical vo;
parameter real gain = 10000;
parameter real offset = 0;
parameter real delay = 160n;
// sampled differential input signal
real v0_val;
// differential ramp signal
real v1_val;
// output signal
real vo_val;
analog begin
// sample the signal
@ (posedge Ph[0]) begin
v0_val = V(v0) ;
end
// sample the signal
@ (negedge Ph[1]) begin
v1_val = V(v1) ;
end
if (Ph[3])
vo_val = 0;
else begin
vo_val = 1.65 - gain*(v0 - v1 - offset);
end
V(vo) <+ absdelay (vo_val, delay);
end
endmodule
As a minimum I'm assuming this should be PH[2] in the "if" condition and
v0 and v1 should be v0_val and v1_val in the vo_val calculation. After
that I'd need more information. You could use $strobe to verify that the
values are being updated when/as you expect. I don't normally use AMS.
It's either straight Verilog-A or Verilog-D for me. I'm assuming you
don't need to deal with interface elements. As a workaround you may be
able to create a digital continuous assignment (outside the analog
block) that splits the bits into individual bits that are used in the
analog block. That would also give them nice descriptive names.

You may also want to check out the forums on "The Designer's Guide"
website. They specialize in AMS discussions.

Cary

Hi Cary,

yes, you are right about Ph[2] and v0_val and v1_val (I just typed in
here that code instead of the actual one).

I tried to create and assignment from, e.g., Ph[2] to Ph2:



---------------
logic PhE;

always begin
PhE = Ph[2];
end

analog begin

@(posedege(PhE) begin
...


-----------------------
But I got an error at the assignment line:
"a net is not a legal lvalue in this context".
I tried also putting that assignment (without the always) inside the
analog block, but I got the same message.
Click to expand...
That's because you need a variable, not a net for an always block
assignment. It's a procedural assignment not a continuous assignment.
For a CA you need to assign to a net. The always method should also
work, but it requires a variable L-value instead of a net.

Try "assign PhE = Ph[2];" and see how that works.

Cary
 
On Jun 1, 12:11 pm, "Cary R." <no-s...@host.spam> wrote:
mm77 wrote:
    logic PhE;

    always begin
      PhE = Ph[2];
    end

The always method should also
work, but it requires a variable L-value instead of a net.
Click to expand...
Unless there are some special AMS rules here, this always block won't
work. It will certainly keep PhE assigned with the value of Ph[2].
But since there is no event control to wait for Ph[2] to change before
doing it again, it will just keep doing it repeatedly and never let
anything else run. This will hang the simulator in this infinite
loop.
 
sharp@cadence.com wrote:
On Jun 1, 12:11 pm, "Cary R." <no-s...@host.spam> wrote:
mm77 wrote:
logic PhE;
always begin
PhE = Ph[2];
end

The always method should also
work, but it requires a variable L-value instead of a net.

Unless there are some special AMS rules here, this always block won't
work. It will certainly keep PhE assigned with the value of Ph[2].
But since there is no event control to wait for Ph[2] to change before
doing it again, it will just keep doing it repeatedly and never let
anything else run. This will hang the simulator in this infinite
loop.
Click to expand...
Good catch Steve! I was thinking always @* which is certainly not what
the OP wrote.

Cary
 
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