Port types

G

Gietek

Guest
Hi,
Do ports always have to be bit, bit_vector, std_logic... etc?
How to implement a port of array type e.g.
Input :in TAB;
type TAB is array(integer) of std_logic_vector;
?
 
Gietek wrote:
Hi,
Do ports always have to be bit, bit_vector, std_logic... etc?
How to implement a port of array type e.g.
Input :in TAB;
type TAB is array(integer) of std_logic_vector;
?
What if I create package?:

package array_std is
type std_logic_array is array(natural range <>, natural range <>)
of std_logic;
end array_std;

Will it produce synthesible logic?
 
Gietek wrote:

Hi,
Do ports always have to be bit, bit_vector, std_logic... etc?
No. My favorite top level types
are std_ulogic, std_logic_vector and unsigned.

How to implement a port of array type e.g.
Input :in TAB;
type TAB is array(integer) of std_logic_vector;

What if I create package?:

package array_std is
type std_logic_array is array(natural range <>, natural range <>) of
std_logic;
end array_std;

Will it produce synthesible logic?
All the vector lengths have to
be determined and in scope at compile time.
I prefer to use generic natural constants for these.
Consider saving the complex data structures
for process variables and architecture signals
that key off of these generic port lengths.

-- Mike Treseler
 

Welcome to EDABoard.com

Sponsor

Back
Top