G
Gietek
Guest
Hi,
Do ports always have to be bit, bit_vector, std_logic... etc?
How to implement a port of array type e.g.
Input :in TAB;
type TAB is array(integer) of std_logic_vector;
?
Do ports always have to be bit, bit_vector, std_logic... etc?
How to implement a port of array type e.g.
Input :in TAB;
type TAB is array(integer) of std_logic_vector;
?