port sizes dont match ?

[dolly]

what is this warning says?
port sizes dont match in port # 1( 16 vs 16)
???

 

[Andy Peters]

"dolly" <shehnaz.tariq@gmail.com> wrote in message news:<88d2f2f73fb9d953b044de1aa313613c@localhost.talkaboutprogramming.com>...

what is this warning says?
port sizes dont match in port # 1( 16 vs 16)

It means your module instantiation has a problem. The module probably
has a vector for one of the ports, but you're connecting it to a
single wire or reg. The most common reason for this is that you
forgot to declare the connecting wire/reg on the higher-level module,
or that you declared it a single-wire (scalar) instead of a vector.
For example,

module lower(foo, bar);
input [1:0] foo;
output [1:0] bar;
endmodule // lower

module upper;

wire [1:0] uno;
wire dos;

lower u1
(.foo (uno),
.bar (dos)); // <- complaint here
endmodule // upper

You get the complaint because the port bar is two bits wide but the
wire that connects to it, dos, is only one bit wide.

It's only a warning (I think it should be an error!) because Verilog
will extend dos to be two bits wide. It's actually legally Verilog
but the tool vendor thought that you most likely made a mistake.

-a