port names in vhdl

[rajan]

Hi,

Is it possible to have the same names of the ports in top-level entity as in
the components. e.g.

entity U_1 is
port (A, B : in std_logic;
Cout: out std_logic
);
end entity;

architecture example of U_1 is
component C_1
port (A, B : in std_logic;
Y : out std_logic
);
end component;

...........

u1 : C_1 port map (A => A, B => B, Y => Cout) ;


Is it possible to do like this. Though this is just an example so, please
ignore the syntax.

Thanks in advance.

 

[Ralf Hildebrandt]

rajan wrote:

Is it possible to have the same names of the ports in top-level entity as in
the components.

Yes it is possible and it is quite useful for good readable code. Just
try it. - Or what is your question? (I can't see any question mark in
your posting. ;-) )

Ralf

 

[anupam]

Hi Rajan,
Yes it is possible.
Anupam garg