Port mode is incompatible error

O

ohaqqi@gmail.com

Guest
I keep getting Error on line 31: Port mode is incompatible with
declaration: A

Same thing for B.

This is line 31 that gives error: reg [15:0] A,B;

Here is the code:
************************************************************************************

module alu16(A,B,C,alu_code,overflow);

/****************************************************
16 bit arithmetic logic unit

parameter:
A.........16-bit A bidirectional
B.........16-bit B input
alu_code..5-bit operation to perform
C.........16-bit bit result output
overflow..overflow status (used for signed operations)
****************************************************/
inout [15:0] A;
input [15:0] B;
input [4:0] alu_code;
output [15:0] C;
output overflow;

//internal nodes

reg [15:0] A,B;
reg [15:0] C;
reg overflow;

always @ (A or B or alu_code) begin

//ARITHMETIC OPERATIONS

if(alu_code[4:3] == 2'b00) begin
case (alu_code[2:0])
3'b000:C = !((!A + 1) + (!B + 1) + 1); //signed 2's complement
addition
3'b001:C = A + B;
3'b010:C = !((!A + 1) - (!B + 1) + 1); //signed 2's complement
subtraction
3'b011:C = A - B;
3'b100:C = A + 1;
3'b101:C = A - 1;
default:C = 8'bx;
endcase
overflow = C[15]^C[14];
end

//LOGIC OPERATIONS

else if(alu_code[4:3] == 2'b01) begin
case (alu_code[2:0])
3'b000:C = A && B;
3'b001:C = A || B;
3'b010:C = ((!A)&&(B) || (A)&&(!B));
3'b000:C = !A;
default:C = 8'bx;
endcase
end

//SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic
shifts in Verilog2001 and SystemVerilog)

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;
else if(B[3:0] == 4'b0101) A = A << 5;
else if(B[3:0] == 4'b0110) A = A << 6;
else if(B[3:0] == 4'b0111) A = A << 7;
else if(B[3:0] == 4'b1000) A = A << 8;
else if(B[3:0] == 4'b1001) A = A << 9;
else if(B[3:0] == 4'b1010) A = A << 10;
else if(B[3:0] == 4'b1011) A = A << 11;
else if(B[3:0] == 4'b1100) A = A << 12;
else if(B[3:0] == 4'b1101) A = A << 13;
else if(B[3:0] == 4'b1110) A = A << 14;
else if(B[3:0] == 4'b1111) A = A << 15;
3'b001:
if(B[3:0] == 4'b0000) A = A >> 0;
else if(B[3:0] == 4'b0001) A = A >> 1;
else if(B[3:0] == 4'b0010) A = A >> 2;
else if(B[3:0] == 4'b0011) A = A >> 3;
else if(B[3:0] == 4'b0100) A = A >> 4;
else if(B[3:0] == 4'b0101) A = A >> 5;
else if(B[3:0] == 4'b0110) A = A >> 6;
else if(B[3:0] == 4'b0111) A = A >> 7;
else if(B[3:0] == 4'b1000) A = A >> 8;
else if(B[3:0] == 4'b1001) A = A >> 9;
else if(B[3:0] == 4'b1010) A = A >> 10;
else if(B[3:0] == 4'b1011) A = A >> 11;
else if(B[3:0] == 4'b1100) A = A >> 12;
else if(B[3:0] == 4'b1101) A = A >> 13;
else if(B[3:0] == 4'b1110) A = A >> 14;
else if(B[3:0] == 4'b1111) A = A >> 15;
3'b010:
if(B[3:0] == 4'b0000) A = A <<< 0;
else if(B[3:0] == 4'b0001) A = A <<< 1;
else if(B[3:0] == 4'b0010) A = A <<< 2;
else if(B[3:0] == 4'b0011) A = A <<< 3;
else if(B[3:0] == 4'b0100) A = A <<< 4;
else if(B[3:0] == 4'b0101) A = A <<< 5;
else if(B[3:0] == 4'b0110) A = A <<< 6;
else if(B[3:0] == 4'b0111) A = A <<< 7;
else if(B[3:0] == 4'b1000) A = A <<< 8;
else if(B[3:0] == 4'b1001) A = A <<< 9;
else if(B[3:0] == 4'b1010) A = A <<< 10;
else if(B[3:0] == 4'b1011) A = A <<< 11;
else if(B[3:0] == 4'b1100) A = A <<< 12;
else if(B[3:0] == 4'b1101) A = A <<< 13;
else if(B[3:0] == 4'b1110) A = A <<< 14;
else if(B[3:0] == 4'b1111) A = A <<< 15;
3'b000:
if(B[3:0] == 4'b0000) A = A >>> 0;
else if(B[3:0] == 4'b0001) A = A >>> 1;
else if(B[3:0] == 4'b0010) A = A >>> 2;
else if(B[3:0] == 4'b0011) A = A >>> 3;
else if(B[3:0] == 4'b0100) A = A >>> 4;
else if(B[3:0] == 4'b0101) A = A >>> 5;
else if(B[3:0] == 4'b0110) A = A >>> 6;
else if(B[3:0] == 4'b0111) A = A >>> 7;
else if(B[3:0] == 4'b1000) A = A >>> 8;
else if(B[3:0] == 4'b1001) A = A >>> 9;
else if(B[3:0] == 4'b1010) A = A >>> 10;
else if(B[3:0] == 4'b1011) A = A >>> 11;
else if(B[3:0] == 4'b1100) A = A >>> 12;
else if(B[3:0] == 4'b1101) A = A >>> 13;
else if(B[3:0] == 4'b1110) A = A >>> 14;
else if(B[3:0] == 4'b1111) A = A >>> 15;
endcase
end
end

//SET CONDITION OPERATIONS
endmodule
 
Inout can't be a "reg". Use a temporary reg/logic and assign it to the
inout if you really have to use inout. Inouts usually are not
preferred, in this design you may not even need it.

Regards
Ajeetha, CVC
www.noveldv.com
 
Ok, I made the change( to make A an input and an internal wire, not
register), but now it gives this error:

** Error: alu16.v(70): (vlog-2110) Illegal reference to net "A".

For every line of code that tries to shift, for example:

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;

I am trying shift vector A by the amount contained in B[3:0] -- between
0 and 15. Any help would be much appreciated.


/////////////////////////////////////////////////////////////////////////////
ohaqqi@gmail.com wrote:
I keep getting Error on line 31: Port mode is incompatible with
declaration: A

Same thing for B.

This is line 31 that gives error: reg [15:0] A,B;

Here is the code:
************************************************************************************

module alu16(A,B,C,alu_code,overflow);

/****************************************************
16 bit arithmetic logic unit

parameter:
A.........16-bit A bidirectional
B.........16-bit B input
alu_code..5-bit operation to perform
C.........16-bit bit result output
overflow..overflow status (used for signed operations)
****************************************************/
inout [15:0] A;
input [15:0] B;
input [4:0] alu_code;
output [15:0] C;
output overflow;

//internal nodes

reg [15:0] A,B;
reg [15:0] C;
reg overflow;

always @ (A or B or alu_code) begin

//ARITHMETIC OPERATIONS

if(alu_code[4:3] == 2'b00) begin
case (alu_code[2:0])
3'b000:C = !((!A + 1) + (!B + 1) + 1); //signed 2's complement
addition
3'b001:C = A + B;
3'b010:C = !((!A + 1) - (!B + 1) + 1); //signed 2's complement
subtraction
3'b011:C = A - B;
3'b100:C = A + 1;
3'b101:C = A - 1;
default:C = 8'bx;
endcase
overflow = C[15]^C[14];
end

//LOGIC OPERATIONS

else if(alu_code[4:3] == 2'b01) begin
case (alu_code[2:0])
3'b000:C = A && B;
3'b001:C = A || B;
3'b010:C = ((!A)&&(B) || (A)&&(!B));
3'b000:C = !A;
default:C = 8'bx;
endcase
end

//SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic
shifts in Verilog2001 and SystemVerilog)

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;
else if(B[3:0] == 4'b0101) A = A << 5;
else if(B[3:0] == 4'b0110) A = A << 6;
else if(B[3:0] == 4'b0111) A = A << 7;
else if(B[3:0] == 4'b1000) A = A << 8;
else if(B[3:0] == 4'b1001) A = A << 9;
else if(B[3:0] == 4'b1010) A = A << 10;
else if(B[3:0] == 4'b1011) A = A << 11;
else if(B[3:0] == 4'b1100) A = A << 12;
else if(B[3:0] == 4'b1101) A = A << 13;
else if(B[3:0] == 4'b1110) A = A << 14;
else if(B[3:0] == 4'b1111) A = A << 15;
3'b001:
if(B[3:0] == 4'b0000) A = A >> 0;
else if(B[3:0] == 4'b0001) A = A >> 1;
else if(B[3:0] == 4'b0010) A = A >> 2;
else if(B[3:0] == 4'b0011) A = A >> 3;
else if(B[3:0] == 4'b0100) A = A >> 4;
else if(B[3:0] == 4'b0101) A = A >> 5;
else if(B[3:0] == 4'b0110) A = A >> 6;
else if(B[3:0] == 4'b0111) A = A >> 7;
else if(B[3:0] == 4'b1000) A = A >> 8;
else if(B[3:0] == 4'b1001) A = A >> 9;
else if(B[3:0] == 4'b1010) A = A >> 10;
else if(B[3:0] == 4'b1011) A = A >> 11;
else if(B[3:0] == 4'b1100) A = A >> 12;
else if(B[3:0] == 4'b1101) A = A >> 13;
else if(B[3:0] == 4'b1110) A = A >> 14;
else if(B[3:0] == 4'b1111) A = A >> 15;
3'b010:
if(B[3:0] == 4'b0000) A = A <<< 0;
else if(B[3:0] == 4'b0001) A = A <<< 1;
else if(B[3:0] == 4'b0010) A = A <<< 2;
else if(B[3:0] == 4'b0011) A = A <<< 3;
else if(B[3:0] == 4'b0100) A = A <<< 4;
else if(B[3:0] == 4'b0101) A = A <<< 5;
else if(B[3:0] == 4'b0110) A = A <<< 6;
else if(B[3:0] == 4'b0111) A = A <<< 7;
else if(B[3:0] == 4'b1000) A = A <<< 8;
else if(B[3:0] == 4'b1001) A = A <<< 9;
else if(B[3:0] == 4'b1010) A = A <<< 10;
else if(B[3:0] == 4'b1011) A = A <<< 11;
else if(B[3:0] == 4'b1100) A = A <<< 12;
else if(B[3:0] == 4'b1101) A = A <<< 13;
else if(B[3:0] == 4'b1110) A = A <<< 14;
else if(B[3:0] == 4'b1111) A = A <<< 15;
3'b000:
if(B[3:0] == 4'b0000) A = A >>> 0;
else if(B[3:0] == 4'b0001) A = A >>> 1;
else if(B[3:0] == 4'b0010) A = A >>> 2;
else if(B[3:0] == 4'b0011) A = A >>> 3;
else if(B[3:0] == 4'b0100) A = A >>> 4;
else if(B[3:0] == 4'b0101) A = A >>> 5;
else if(B[3:0] == 4'b0110) A = A >>> 6;
else if(B[3:0] == 4'b0111) A = A >>> 7;
else if(B[3:0] == 4'b1000) A = A >>> 8;
else if(B[3:0] == 4'b1001) A = A >>> 9;
else if(B[3:0] == 4'b1010) A = A >>> 10;
else if(B[3:0] == 4'b1011) A = A >>> 11;
else if(B[3:0] == 4'b1100) A = A >>> 12;
else if(B[3:0] == 4'b1101) A = A >>> 13;
else if(B[3:0] == 4'b1110) A = A >>> 14;
else if(B[3:0] == 4'b1111) A = A >>> 15;
endcase
end
end

//SET CONDITION OPERATIONS
endmodule
Click to expand...
 
Do you also have to do synthesis for this homework assignment?
Which university is it?

Utku

ohaqqi@gmail.com wrote:
Ok, I made the change( to make A an input and an internal wire, not
register), but now it gives this error:

** Error: alu16.v(70): (vlog-2110) Illegal reference to net "A".

For every line of code that tries to shift, for example:

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;

I am trying shift vector A by the amount contained in B[3:0] -- between
0 and 15. Any help would be much appreciated.


/////////////////////////////////////////////////////////////////////////////
ohaqqi@gmail.com wrote:
I keep getting Error on line 31: Port mode is incompatible with
declaration: A

Same thing for B.

This is line 31 that gives error: reg [15:0] A,B;

Here is the code:
************************************************************************************

module alu16(A,B,C,alu_code,overflow);

/****************************************************
16 bit arithmetic logic unit

parameter:
A.........16-bit A bidirectional
B.........16-bit B input
alu_code..5-bit operation to perform
C.........16-bit bit result output
overflow..overflow status (used for signed operations)
****************************************************/
inout [15:0] A;
input [15:0] B;
input [4:0] alu_code;
output [15:0] C;
output overflow;

//internal nodes

reg [15:0] A,B;
reg [15:0] C;
reg overflow;

always @ (A or B or alu_code) begin

//ARITHMETIC OPERATIONS

if(alu_code[4:3] == 2'b00) begin
case (alu_code[2:0])
3'b000:C = !((!A + 1) + (!B + 1) + 1); //signed 2's complement
addition
3'b001:C = A + B;
3'b010:C = !((!A + 1) - (!B + 1) + 1); //signed 2's complement
subtraction
3'b011:C = A - B;
3'b100:C = A + 1;
3'b101:C = A - 1;
default:C = 8'bx;
endcase
overflow = C[15]^C[14];
end

//LOGIC OPERATIONS

else if(alu_code[4:3] == 2'b01) begin
case (alu_code[2:0])
3'b000:C = A && B;
3'b001:C = A || B;
3'b010:C = ((!A)&&(B) || (A)&&(!B));
3'b000:C = !A;
default:C = 8'bx;
endcase
end

//SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic
shifts in Verilog2001 and SystemVerilog)

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;
else if(B[3:0] == 4'b0101) A = A << 5;
else if(B[3:0] == 4'b0110) A = A << 6;
else if(B[3:0] == 4'b0111) A = A << 7;
else if(B[3:0] == 4'b1000) A = A << 8;
else if(B[3:0] == 4'b1001) A = A << 9;
else if(B[3:0] == 4'b1010) A = A << 10;
else if(B[3:0] == 4'b1011) A = A << 11;
else if(B[3:0] == 4'b1100) A = A << 12;
else if(B[3:0] == 4'b1101) A = A << 13;
else if(B[3:0] == 4'b1110) A = A << 14;
else if(B[3:0] == 4'b1111) A = A << 15;
3'b001:
if(B[3:0] == 4'b0000) A = A >> 0;
else if(B[3:0] == 4'b0001) A = A >> 1;
else if(B[3:0] == 4'b0010) A = A >> 2;
else if(B[3:0] == 4'b0011) A = A >> 3;
else if(B[3:0] == 4'b0100) A = A >> 4;
else if(B[3:0] == 4'b0101) A = A >> 5;
else if(B[3:0] == 4'b0110) A = A >> 6;
else if(B[3:0] == 4'b0111) A = A >> 7;
else if(B[3:0] == 4'b1000) A = A >> 8;
else if(B[3:0] == 4'b1001) A = A >> 9;
else if(B[3:0] == 4'b1010) A = A >> 10;
else if(B[3:0] == 4'b1011) A = A >> 11;
else if(B[3:0] == 4'b1100) A = A >> 12;
else if(B[3:0] == 4'b1101) A = A >> 13;
else if(B[3:0] == 4'b1110) A = A >> 14;
else if(B[3:0] == 4'b1111) A = A >> 15;
3'b010:
if(B[3:0] == 4'b0000) A = A <<< 0;
else if(B[3:0] == 4'b0001) A = A <<< 1;
else if(B[3:0] == 4'b0010) A = A <<< 2;
else if(B[3:0] == 4'b0011) A = A <<< 3;
else if(B[3:0] == 4'b0100) A = A <<< 4;
else if(B[3:0] == 4'b0101) A = A <<< 5;
else if(B[3:0] == 4'b0110) A = A <<< 6;
else if(B[3:0] == 4'b0111) A = A <<< 7;
else if(B[3:0] == 4'b1000) A = A <<< 8;
else if(B[3:0] == 4'b1001) A = A <<< 9;
else if(B[3:0] == 4'b1010) A = A <<< 10;
else if(B[3:0] == 4'b1011) A = A <<< 11;
else if(B[3:0] == 4'b1100) A = A <<< 12;
else if(B[3:0] == 4'b1101) A = A <<< 13;
else if(B[3:0] == 4'b1110) A = A <<< 14;
else if(B[3:0] == 4'b1111) A = A <<< 15;
3'b000:
if(B[3:0] == 4'b0000) A = A >>> 0;
else if(B[3:0] == 4'b0001) A = A >>> 1;
else if(B[3:0] == 4'b0010) A = A >>> 2;
else if(B[3:0] == 4'b0011) A = A >>> 3;
else if(B[3:0] == 4'b0100) A = A >>> 4;
else if(B[3:0] == 4'b0101) A = A >>> 5;
else if(B[3:0] == 4'b0110) A = A >>> 6;
else if(B[3:0] == 4'b0111) A = A >>> 7;
else if(B[3:0] == 4'b1000) A = A >>> 8;
else if(B[3:0] == 4'b1001) A = A >>> 9;
else if(B[3:0] == 4'b1010) A = A >>> 10;
else if(B[3:0] == 4'b1011) A = A >>> 11;
else if(B[3:0] == 4'b1100) A = A >>> 12;
else if(B[3:0] == 4'b1101) A = A >>> 13;
else if(B[3:0] == 4'b1110) A = A >>> 14;
else if(B[3:0] == 4'b1111) A = A >>> 15;
endcase
end
end

//SET CONDITION OPERATIONS
endmodule
Click to expand...
 
Yes I will use ADK to synthesize.

utku.ozcan@gmail.com wrote:
Do you also have to do synthesis for this homework assignment?
Which university is it?

Utku

ohaqqi@gmail.com wrote:
Ok, I made the change( to make A an input and an internal wire, not
register), but now it gives this error:

** Error: alu16.v(70): (vlog-2110) Illegal reference to net "A".

For every line of code that tries to shift, for example:

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;

I am trying shift vector A by the amount contained in B[3:0] -- between
0 and 15. Any help would be much appreciated.


/////////////////////////////////////////////////////////////////////////////
ohaqqi@gmail.com wrote:
I keep getting Error on line 31: Port mode is incompatible with
declaration: A

Same thing for B.

This is line 31 that gives error: reg [15:0] A,B;

Here is the code:
************************************************************************************

module alu16(A,B,C,alu_code,overflow);

/****************************************************
16 bit arithmetic logic unit

parameter:
A.........16-bit A bidirectional
B.........16-bit B input
alu_code..5-bit operation to perform
C.........16-bit bit result output
overflow..overflow status (used for signed operations)
****************************************************/
inout [15:0] A;
input [15:0] B;
input [4:0] alu_code;
output [15:0] C;
output overflow;

//internal nodes

reg [15:0] A,B;
reg [15:0] C;
reg overflow;

always @ (A or B or alu_code) begin

//ARITHMETIC OPERATIONS

if(alu_code[4:3] == 2'b00) begin
case (alu_code[2:0])
3'b000:C = !((!A + 1) + (!B + 1) + 1); //signed 2's complement
addition
3'b001:C = A + B;
3'b010:C = !((!A + 1) - (!B + 1) + 1); //signed 2's complement
subtraction
3'b011:C = A - B;
3'b100:C = A + 1;
3'b101:C = A - 1;
default:C = 8'bx;
endcase
overflow = C[15]^C[14];
end

//LOGIC OPERATIONS

else if(alu_code[4:3] == 2'b01) begin
case (alu_code[2:0])
3'b000:C = A && B;
3'b001:C = A || B;
3'b010:C = ((!A)&&(B) || (A)&&(!B));
3'b000:C = !A;
default:C = 8'bx;
endcase
end

//SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic
shifts in Verilog2001 and SystemVerilog)

else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;
else if(B[3:0] == 4'b0101) A = A << 5;
else if(B[3:0] == 4'b0110) A = A << 6;
else if(B[3:0] == 4'b0111) A = A << 7;
else if(B[3:0] == 4'b1000) A = A << 8;
else if(B[3:0] == 4'b1001) A = A << 9;
else if(B[3:0] == 4'b1010) A = A << 10;
else if(B[3:0] == 4'b1011) A = A << 11;
else if(B[3:0] == 4'b1100) A = A << 12;
else if(B[3:0] == 4'b1101) A = A << 13;
else if(B[3:0] == 4'b1110) A = A << 14;
else if(B[3:0] == 4'b1111) A = A << 15;
3'b001:
if(B[3:0] == 4'b0000) A = A >> 0;
else if(B[3:0] == 4'b0001) A = A >> 1;
else if(B[3:0] == 4'b0010) A = A >> 2;
else if(B[3:0] == 4'b0011) A = A >> 3;
else if(B[3:0] == 4'b0100) A = A >> 4;
else if(B[3:0] == 4'b0101) A = A >> 5;
else if(B[3:0] == 4'b0110) A = A >> 6;
else if(B[3:0] == 4'b0111) A = A >> 7;
else if(B[3:0] == 4'b1000) A = A >> 8;
else if(B[3:0] == 4'b1001) A = A >> 9;
else if(B[3:0] == 4'b1010) A = A >> 10;
else if(B[3:0] == 4'b1011) A = A >> 11;
else if(B[3:0] == 4'b1100) A = A >> 12;
else if(B[3:0] == 4'b1101) A = A >> 13;
else if(B[3:0] == 4'b1110) A = A >> 14;
else if(B[3:0] == 4'b1111) A = A >> 15;
3'b010:
if(B[3:0] == 4'b0000) A = A <<< 0;
else if(B[3:0] == 4'b0001) A = A <<< 1;
else if(B[3:0] == 4'b0010) A = A <<< 2;
else if(B[3:0] == 4'b0011) A = A <<< 3;
else if(B[3:0] == 4'b0100) A = A <<< 4;
else if(B[3:0] == 4'b0101) A = A <<< 5;
else if(B[3:0] == 4'b0110) A = A <<< 6;
else if(B[3:0] == 4'b0111) A = A <<< 7;
else if(B[3:0] == 4'b1000) A = A <<< 8;
else if(B[3:0] == 4'b1001) A = A <<< 9;
else if(B[3:0] == 4'b1010) A = A <<< 10;
else if(B[3:0] == 4'b1011) A = A <<< 11;
else if(B[3:0] == 4'b1100) A = A <<< 12;
else if(B[3:0] == 4'b1101) A = A <<< 13;
else if(B[3:0] == 4'b1110) A = A <<< 14;
else if(B[3:0] == 4'b1111) A = A <<< 15;
3'b000:
if(B[3:0] == 4'b0000) A = A >>> 0;
else if(B[3:0] == 4'b0001) A = A >>> 1;
else if(B[3:0] == 4'b0010) A = A >>> 2;
else if(B[3:0] == 4'b0011) A = A >>> 3;
else if(B[3:0] == 4'b0100) A = A >>> 4;
else if(B[3:0] == 4'b0101) A = A >>> 5;
else if(B[3:0] == 4'b0110) A = A >>> 6;
else if(B[3:0] == 4'b0111) A = A >>> 7;
else if(B[3:0] == 4'b1000) A = A >>> 8;
else if(B[3:0] == 4'b1001) A = A >>> 9;
else if(B[3:0] == 4'b1010) A = A >>> 10;
else if(B[3:0] == 4'b1011) A = A >>> 11;
else if(B[3:0] == 4'b1100) A = A >>> 12;
else if(B[3:0] == 4'b1101) A = A >>> 13;
else if(B[3:0] == 4'b1110) A = A >>> 14;
else if(B[3:0] == 4'b1111) A = A >>> 15;
endcase
end
end

//SET CONDITION OPERATIONS
endmodule
Click to expand...
 
ohaqqi@gmail.com wrote:

Ok, I made the change( to make A an input and an internal wire, not
register), but now it gives this error:
** Error: alu16.v(70): (vlog-2110) Illegal reference to net "A".
For every line of code that tries to shift, for example:
Click to expand...
Hint: you have to be explicit about *when* you drive the inout.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
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