Port Map Trouble

[nfirtaps]

Hi,
I am getting warnings indicating that my port mapped inputs/outputs
are not being used. Here is my basic syntax can someone tell me if
this is correct or incorrect?

entity forum_question is
port (
my_input_in : in std_logic;
my_output_out : out std_logic;
);
end forum_question;

architecture behavioral of forum_question is
signal my_input_wire, my_output_wire : std_logic;

component black_box
port (
input : in std_logic;
output : out std_logic;
);
end component

begin

ibuf1 : ibuf
port map(
o => my_input_wire;
i => my_input_in
);

obuf1 : ibuf
port map(
o => my_output_out;
i => my_output_wire
);

warnings_are_here : black_box
port map(
input => my_input_wire; -- Warning input is never used
output => my_output_wire;-- Warning output is never used
);

end behavioral;

Does anyone see anything wrong with this type of program?

Thanks

 

[Dave Pollum]

nfirtaps wrote:

Hi,
I am getting warnings indicating that my port mapped inputs/outputs
are not being used. Here is my basic syntax can someone tell me if
this is correct or incorrect?

entity forum_question is
port (
my_input_in : in std_logic;
my_output_out : out std_logic;
);
end forum_question;

architecture behavioral of forum_question is
signal my_input_wire, my_output_wire : std_logic;

component black_box
port (
input : in std_logic;
output : out std_logic;
);
end component

begin

ibuf1 : ibuf
port map(
o => my_input_wire;
i => my_input_in
);

obuf1 : ibuf
port map(
o => my_output_out;
i => my_output_wire
);

warnings_are_here : black_box
port map(
input => my_input_wire; -- Warning input is never used
output => my_output_wire;-- Warning output is never used
);

end behavioral;

Does anyone see anything wrong with this type of program?

Thanks

Move your signal declarations _after_ the component declaration and see
if that works.
HTH - Dave Pollum

 

[anupam.jain21@gmail.com]

Dave Pollum wrote:

nfirtaps wrote:
Hi,
I am getting warnings indicating that my port mapped inputs/outputs
are not being used. Here is my basic syntax can someone tell me if
this is correct or incorrect?

entity forum_question is
port (
my_input_in : in std_logic;
my_output_out : out std_logic;
);
end forum_question;

architecture behavioral of forum_question is
signal my_input_wire, my_output_wire : std_logic;

component black_box
port (
input : in std_logic;
output : out std_logic;
);
end component

begin

ibuf1 : ibuf
port map(
o => my_input_wire;
i => my_input_in
);

obuf1 : ibuf
port map(
o => my_output_out;
i => my_output_wire
);

warnings_are_here : black_box
port map(
input => my_input_wire; -- Warning input is never used
output => my_output_wire;-- Warning output is never used
);

end behavioral;

Does anyone see anything wrong with this type of program?

Thanks

hi,
The Port maps are seperated by commas and not semi colon and no comma
at the end of last port map.
This is all i could see wrong at a first glance.

regrads,
Anupam Jain