Port Map Array

I am attempting to take a 2 dimentional array, and port map it to a
package to do a sort operation, and finally have it output the sorted
array. Here is the array definition within my main module architecture.


type SORT_HI_ARRAY is array (1 to 9) of std_logic_vector(10 downto 0) ;

signal SORT_ARRAY : SORT_HI_ARRAY ;

Instead of repeating the sort routine multiple times within my main
vhdl module (for multiple sorts), I would like to pass on (port map)
the array to another entity or package to do the work, and receive back
the sorted array. I can not use a function to do the sort within my
main module, since a function can only have one output.

If it can be done, my module will pass the array and a Sort_Now signal
to an external package or entity, and get back the sorted array.

Thanks ahead of time.

 

[Reiner Huober]

Marvin.Stoltman@L-3com.com schrieb:

I am attempting to take a 2 dimentional array, and port map it to a
package to do a sort operation, and finally have it output the sorted
array. Here is the array definition within my main module architecture.


type SORT_HI_ARRAY is array (1 to 9) of std_logic_vector(10 downto 0) ;

signal SORT_ARRAY : SORT_HI_ARRAY ;

Instead of repeating the sort routine multiple times within my main
vhdl module (for multiple sorts), I would like to pass on (port map)
the array to another entity or package to do the work, and receive back
the sorted array.

Yes, this is strait forward. You can use two ports A,B. However, you
have to add control information. You can use A'event and the sort it in
the next delta cycle and drive B then.

entity sorter
.... PORT A: in SORT_HI_ARRAY;
PORT B: out SORT_HI_ARRAY;
...
architecture bubble of sorter is
....
process bubblesort(A)
type SORT_HI_ARRAY_INT is array(SORT_HI_ARRAY'range) of integer;
variable X: SORT_HI_ARRAY;
variable Xint:
begin
X:=A;
--- convert X to Xint (using to_integer(signed(X(i))) o so)
--- add here well known bubblesort code of Xint
--- convert Xint to X (using to_signed(Xint(i))
B<=X;
end bubblesort;
end bubble;

I can not use a function to do the sort within my
main module, since a function can only have one output.

The (sort) function could hav a std_logic_vector as return value.

function quicksort(A: std_logic_vector) return std_logic_vector ...

can be easily defined in VHDL.

You can also use a procedure.
VHDL'93 allows impure functions changing global values (not
recommended).


END Hubble;

 

[Reiner Huober]

Reiner Huober schrieb:

Marvin.Stoltman@L-3com.com schrieb:

I am attempting to take a 2 dimentional array, and port map it to a
package to do a sort operation, and finally have it output the sorted
array. Here is the array definition within my main module architecture.


type SORT_HI_ARRAY is array (1 to 9) of std_logic_vector(10 downto 0) ;

signal SORT_ARRAY : SORT_HI_ARRAY ;

Instead of repeating the sort routine multiple times within my main
vhdl module (for multiple sorts), I would like to pass on (port map)
the array to another entity or package to do the work, and receive back
the sorted array.


Yes, this is strait forward. You can use two ports A,B. However, you
have to add control information. You can use A'event and the sort it in
the next delta cycle and drive B then.

entity sorter
... PORT A: in SORT_HI_ARRAY;
PORT B: out SORT_HI_ARRAY;
..
architecture bubble of sorter is
...
process bubblesort(A)
type SORT_HI_ARRAY_INT is array(SORT_HI_ARRAY'range) of integer;
variable X: SORT_HI_ARRAY;
variable Xint:
begin
X:=A;
--- convert X to Xint (using to_integer(signed(X(i))) o so)
--- add here well known bubblesort code of Xint
--- convert Xint to X (using to_signed(Xint(i))
B<=X;
end bubblesort;
end bubble;

I can not use a function to do the sort within my
main module, since a function can only have one output.

The (sort) function could hav a std_logic_vector as return value.

function quicksort(A: std_logic_vector) return std_logic_vector ...

can be easily defined in VHDL.

You can also use a procedure.
VHDL'93 allows impure functions changing global values (not
recommended).


END Hubble;

BTW, do not assign SORT_ARRAY to the ports A and Bof the sorter. You
will have to define a sort event. This is due to signal resolution. You
must fill the array with predefined values and then the sorter must
sort it. The se are two drivers so that you gat nothing. Also, if you
lack an event, the simulation will cycle.

If you must have a single signal, you must also have a single process
which drives SORT_ARRAY.

architecture ...
Signal Tmp_Out: SORT_HI_ARRAY_TYPE
Sorter_I: Sorter(A => SORT_ARRAY, B=> Tmp_Out);

--- SORT_ARRAY will be sorted on clock
process
begin
WAIT UNTIL rising_edge(CLK):
SORT_ARRAY<= ... : -- any method to get SORT_ARRAY
--- allow one delta cycle for sorter, then Tmp_out is set
WAIT FOR 0 ns
---- now Tmp_Out contains the sorted array, we can assign
SORT_ARRAY
SORT_ARRAY<=Tmp_Out;
end;

This process contains the only driver . However consider
a) using two different signals for input and output
b) using a shared variable (VHDL'93)

END Hubble.

 

[Reiner Huober]

Marvin.Stoltman@L-3com.com schrieb:

I am attempting to take a 2 dimentional array, and port map it to a
package to do a sort operation, and finally have it output the sorted
array. Here is the array definition within my main module architecture.


type SORT_HI_ARRAY is array (1 to 9) of std_logic_vector(10 downto 0) ;

signal SORT_ARRAY : SORT_HI_ARRAY ;

Instead of repeating the sort routine multiple times within my main
vhdl module (for multiple sorts), I would like to pass on (port map)
the array to another entity or package to do the work, and receive back
the sorted array. I can not use a function to do the sort within my
main module, since a function can only have one output.

If it can be done, my module will pass the array and a Sort_Now signal
to an external package or entity, and get back the sorted array.

Thanks ahead of time.

Having thought a little bit further, it turns out that you should have
two signals in the sorter entity, one enable and one sort_now signal.
Then you can have an INOUT port. If enable is false ('0'), you mus
assign (others => (others => 'Z')) to the port. The enable and the
sort_now signal should never be asserted at the samte time:

entity MySorter is
....
PORT SORT_ARRAY: inout SORT_HI_ARRAY;
PORT Enable: in std_logic;
PORT Sort_Now: in std_logic; -- sort at rising edge of Sort_Now
end;

architecture bubble of MySorter is
function bubblesort(A: SORT_HI_ARRAY) return SORT_HI_ARRAY is
begin
--- left as an exercise
end;
Signal Internal_Sort_Array: SORT_HI_ARRAY;
begin
SORT_ARRAY<=Internal_Sort_Array when Enable='1' else (others =>
(others => 'Z'));
assert Enable/='1' or not rising_edge(Sort_Now)
report "Enable and Sort_Now conflict" severity failure;
DoSort: process(Sort_Now)
begin
if rising_edge(Sort_Now) then
Internal_Sort_Array<=bubblesort(SORT_ARRAY);
end of;
end;
end bubble;

The client must set Enable to '0'. It can then assign input values to
the SORT_ARRAY signal and assert Sort_Now. Afterwards, it can deassert
Sort_Now and set Enable '1' and SORT_ARRAY to (others=> (others =>
'Z')). Then the sort result apperas in SORT_ARRAY

The question is, if this additional logic is worth using only one
signal for input values and result.

END Hubble.