port declaration

[Andy Luotto]

I am compiling a module withj the following port declaration

module periph_sys (

// APB I/F
pclk_i,
presetn_i,
paddr_i[31:0],
prdata_o[31:0],
-> I should have used this:
-> paddr_i,
-> prdata_o, <<
->
);

// APB I/F
input pclk_i;
input presetn_i;
input [31:0] paddr_i;
output [31:0] prdata_o;

by mistake I put the vector length in the port list but I can
successfully compile. Which makes me puzzled: should not this be a
syntax error? Or it is just because verilog 2K allows vector notation
in the port list?

Thanks for your help

Cheers

 

Verilog 2001

 

chrisbw@gmail.com wrote:

Verilog 2001

No, in Verilog-2001 ANSI-C style port declarations, these would all
have to be full declarations with port directions, with the vector
range before rather than after the identifier.

These are Verilog-1995 declarations. In Verilog-1995, you can declare
a module to connect an external port to part of an internal port, or to
a concatenation of internal ports or parts of ports. This declaration
with a range is a declaration of a connection to a part select of the
internal port.
One result of this is that the port does not have an external name, and
cannot be connected by name. You can give it a name by using a named
connection in the module port list. This ability to have ports connect
internally to structural net expressions is rarely used, and most users
don't know about it.