Port declaration for a memory array

[Atul.ee]

Hi,
I am want to declare a port for memory array which is constructed
using flip-flops.
For example:

module test_mode( clk, address, input_bus, mem_out)

input enable;
input [3:0] address;
input [7:0] input_bus;
output [7:0] mem_out [0:15];

reg [7:0] mem_out [0:15];

always @ (posedge clk )
begin
mem_out[address] <= input_bus;
end

endmodule


Please suggest the proper syntax for the synthesizable code.

Regards,
Atul

 

[John_H]

On Feb 3, 4:20 am, "Atul.ee" <atul...@gmail.com> wrote:

Hi,
I am want to declare a port for memory array which is constructed
using flip-flops.
For example:

module test_mode( clk, address, input_bus, mem_out)

input enable;
input [3:0] address;
input [7:0] input_bus;
output [7:0] mem_out [0:15];

reg [7:0] mem_out [0:15];

always @ (posedge clk )
begin
mem_out[address] <= input_bus;
end

endmodule

Please suggest the proper syntax for the synthesizable code.

Regards,
Atul

For Verilog and Verilog2001, there is no syntax. There is no support
for arrays as I/O.

Can anyone comment on SystemVerilog? And is SystemVerilog an option
for you?

 

[Jonathan Bromley]

On Wed, 3 Feb 2010 07:06:06 -0800 (PST), John_H wrote:

For Verilog and Verilog2001, there is no syntax. There is no support
for arrays as I/O.

Can anyone comment on SystemVerilog? And is SystemVerilog an option
for you?

See my post in today's earlier thread
"concatenation with a for loop".
--
Jonathan Bromley

 

[Muzaffer Kal]

On Wed, 3 Feb 2010 01:20:42 -0800 (PST), "Atul.ee" <atul.ee@gmail.com>
wrote:

Hi,
I am want to declare a port for memory array which is constructed
using flip-flops.
For example:

module test_mode( clk, address, input_bus, mem_out)

input enable;
input [3:0] address;
input [7:0] input_bus;
output [7:0] mem_out [0:15];

reg [7:0] mem_out [0:15];

always @ (posedge clk )
begin
mem_out[address] <= input_bus;
end

endmodule


Please suggest the proper syntax for the synthesizable code.

Regards,
Atul

From your code, it's not clear whether you want an "addressable"
entity (suggested by your input address and array operation in the
always block) or access to all the memory simultaneously (suggested by
your mem_out declaration). Perhaps you mean the following:

module test_mode( clk, enable, address, input_bus, mem_out)
input enable;
input [3:0] address;
input [7:0] input_bus;
output [7:0] mem_out;

reg [7:0] memory [0:15];

assign mem_out = memory[address];

always @ (posedge clk )
begin
if (enable) memory[address] <= input_bus;
end

endmodule

If you really want full access to all the memory you'll need to define
a 128 bit output into which you need to slice externally.

ie
output [127:0] mem_out;
assign mem_out = {memory[15], memory[14], ...};
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

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