port connection

[Amir]

Hi,
If I have a module

module m1(input in_1);
input [WIDTH-1:0] in_1;

.....
endmodule

in module top I want to drive zeros to m1,i.e.
module top();
m1 m1 ( .in_1 ((WIDTH)'h0 )); // how can I drive WIDTH bus zeros to
in_1 ?? in the example gave me error...
.....
endmodule

thanks
-Amir

 

[Jonathan Bromley]

On Sun, 15 Mar 2009 01:26:03 -0700 (PDT), Amir wrote:

I want to drive zeros to m1,i.e.
module top();
m1 m1 ( .in_1 ((WIDTH)'h0 )); // how can I drive WIDTH bus zeros to
in_1 ?? in the example gave me error...

This MUST be an FAQ!

Use a replication: {WIDTH{1'b0}}

Or create a wire of the right width, set it to
zero (the constant will automatically be widened
or truncated to the right width) and connect
that wire to the port:

wire [WIDTH-1:0] zero = 0;
m1 m1(.in_1(zero));

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Wed, 18 Mar 2009 03:18:29 -0700 (PDT), karthik wrote:

you can simply use 'b0 in systemVerilog. It fills all the bits with
zero automatically.
You do not require any internal wires and width parameter either.

Careful!!!!!

You can use - note carefully - '0 to do this. It specifies
that the constant has the same width as the target.
But specifying 'b0 makes the constant have the width of
an integer, probably 32 bits. For a zero constant this
is unimportant because the value will be zero-extended
or truncated anyway, but there is a BIG difference
between 'bx and 'x (for example) if the target is
wider than 32 bits. And there is an even bigger
difference between 'b1 and '1 !!!!!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Wed, 18 Mar 2009 10:39:25 +0000, Jonathan Bromley wrote:

Careful!!!!!

Indeed I should be....

there is a BIG difference
between 'bx and 'x (for example) if the target is
wider than 32 bits.

This is not right. I had forgotten that
Verilog-2001 (_not_ SystemVerilog) changed the
rules so that unsized numbers beginning with z or x
are filled to the _expression_ width with the
corresponding z or x bit. This is the same
as SystemVerilog 'x or 'z.

My excuse? This was an incompatible change
between Verilog-95 and Verilog-2001, so I
always carefully avoid unsized 'bx and 'bz.
That's why SystemVerilog 'x, 'z is welcome.

And there is an even bigger
difference between 'b1 and '1 !!!!!

This is indeed true. 'b1 is the numeric
value 1, whereas '1 is all-1s.

Apologies.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[karthik]

Hi

you can simply use 'b0 in systemVerilog. It fills all the bits with
zero automatically.
You do not require any internal wires and width parameter either.

Thanks,
Karthik



On Mar 15, 2:33 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Sun, 15 Mar 2009 01:26:03 -0700 (PDT), Amir wrote:
I want to drive zeros to m1,i.e.
module top();
m1 m1 ( .in_1 ((WIDTH)'h0 )); // how can I drive WIDTH bus zeros to
in_1 ?? in the example gave me error...

This MUST be an FAQ!

Use a replication:  {WIDTH{1'b0}}

Or create a wire of the right width, set it to
zero (the constant will automatically be widened
or truncated to the right width) and connect
that wire to the port:

  wire [WIDTH-1:0] zero = 0;
  m1 m1(.in_1(zero));

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.