Port connection syntax error

[ngsayjoe@gmail.com]

Hi,

Does anyone know what syntax error is the following code?

module ibt20;
wire a,b,c,d,e,f,g,h;
test2 hello ( {a,b,c,}, // Syntax error here
{d,e,f},
g
);
endmodule

module test2( a,b,c,d,e,f,g );
input d,e,f,g;
output a,b,c;

endmodule

When simulate the code in ModelSim, I got the following error:

# ** Error: D:/logicsim/regrun/ibt20.v(4): near "}": syntax error,
unexpected '}', expecting "'{"

However, isn't it a port connection error (different sizes and
connections)? I can't seem to interpret the error reported by ModelSim
and my user. Or is there something I am missing from the Verilog-2001
LRM?


Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

 

Joe
syntax error is because of comma (,) after c in expression {a,b,c,}

-Vinayak

ngsayjoe@gmail.com wrote:

Hi,

Does anyone know what syntax error is the following code?

module ibt20;
wire a,b,c,d,e,f,g,h;
test2 hello ( {a,b,c,}, // Syntax error here
{d,e,f},
g
);
endmodule

module test2( a,b,c,d,e,f,g );
input d,e,f,g;
output a,b,c;

endmodule

When simulate the code in ModelSim, I got the following error:

# ** Error: D:/logicsim/regrun/ibt20.v(4): near "}": syntax error,
unexpected '}', expecting "'{"

However, isn't it a port connection error (different sizes and
connections)? I can't seem to interpret the error reported by ModelSim
and my user. Or is there something I am missing from the Verilog-2001
LRM?


Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

 

[ngsayjoe@gmail.com]

Ohh yeah!! Thank you Vinayak, I missed out that one.

-Joe


vinayaks@gmail.com wrote:

Joe
syntax error is because of comma (,) after c in expression {a,b,c,}

-Vinayak

ngsayjoe@gmail.com wrote:
Hi,

Does anyone know what syntax error is the following code?

module ibt20;
wire a,b,c,d,e,f,g,h;
test2 hello ( {a,b,c,}, // Syntax error here
{d,e,f},
g
);
endmodule

module test2( a,b,c,d,e,f,g );
input d,e,f,g;
output a,b,c;

endmodule

When simulate the code in ModelSim, I got the following error:

# ** Error: D:/logicsim/regrun/ibt20.v(4): near "}": syntax error,
unexpected '}', expecting "'{"

However, isn't it a port connection error (different sizes and
connections)? I can't seem to interpret the error reported by ModelSim
and my user. Or is there something I am missing from the Verilog-2001
LRM?


Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com