port connection problem

[Rain Adelbert]

Hi,

I'm trying to load a SDF description to my gate level design. But, as
the designs are very large it is almost impossible to just try and play
with them. The problem is that the simulator (ModelSim) doesen't find
match for some ports.
For example, in verilog it is:
macro \linphy/macro_1 (...., .I200_({\linphy/I200X [1],\linphy/I200X
[2], \linphy/I200X [3], vddarx, vddarx, vddarx, vddarx, vddarx}), ...);

Specifically, I dont understand how Verilog puts together the
following named port connection: .I200_({\linphy/I200X
[1],\linphy/I200X [2], \linphy/I200X [3], vddarx, vddarx, vddarx,
vddarx, vddarx})

What does the [1], [2], or [3] mean in the specified vector?

Is the I200_ port a bus?

In the SDF file I found the following line:
(INTERCONNECT linphy\/macro_1/I200_\[1\] i_pci_ad_pad30/TEN (0.001::0.001))

Which seems to be incorrect because Modelsim says:
# WARNING: ../test.sdf(6004): Failed to find port 'linphy/macro_1/I200_[1]'

Looking for your help.

Thanks in advance!

Rain

 

[David Jones]

In article <406bdcd4$1_1@news.estpak.ee>,
Rain Adelbert <nospam@nospam.com> wrote:

Hi,

I'm trying to load a SDF description to my gate level design. But, as
the designs are very large it is almost impossible to just try and play
with them. The problem is that the simulator (ModelSim) doesen't find
match for some ports.
For example, in verilog it is:
macro \linphy/macro_1 (...., .I200_({\linphy/I200X [1],\linphy/I200X
[2], \linphy/I200X [3], vddarx, vddarx, vddarx, vddarx, vddarx}), ...);

Specifically, I dont understand how Verilog puts together the
following named port connection: .I200_({\linphy/I200X
[1],\linphy/I200X [2], \linphy/I200X [3], vddarx, vddarx, vddarx,
vddarx, vddarx})

What does the [1], [2], or [3] mean in the specified vector?

Is the I200_ port a bus?

In Verilog, a name that begins with a backslash is an "extended identifier",
which may contain any characters other than whitespace.

So, "\linphy/I200X " is an identifier. Note the space at the end -
this is required, otherwise the following comma would also be considered
part of the identifier.

Extended identifiers often arise during synthesis when the tool either
flattens hierarchy (which seems to have happened in your case) or smashes
buses (leading to names such as "\foo[2] ").

In your specific case, the [1], [2] etc. are standard indexing functions.

In the SDF file I found the following line:
(INTERCONNECT linphy\/macro_1/I200_\[1\] i_pci_ad_pad30/TEN (0.001::0.001))

Which seems to be incorrect because Modelsim says:
# WARNING: ../test.sdf(6004): Failed to find port 'linphy/macro_1/I200_[1]'

You will need to look for a port with that name, or a name close to it.
You likely won't find it exactly, but the difference will tell you what
went wrong.

 

[Steven Sharp]

Rain Adelbert <nospam@nospam.com> wrote in message news:<406bdcd4$1_1@news.estpak.ee>...

Specifically, I dont understand how Verilog puts together the
following named port connection: .I200_({\linphy/I200X
[1],\linphy/I200X [2], \linphy/I200X [3], vddarx, vddarx, vddarx,
vddarx, vddarx})

What does the [1], [2], or [3] mean in the specified vector?

They are bit-selects of the vector object named "linphy/I200X". The
space before the bit select is to end the escaped name that is allowing
the "/" character to appear in the name. Without the space, you would
have names like "linphy/I200X[1]", i.e. the bracketed index would be
treated as part of the name string rather than a bit-select. Aside from
the escaped name syntax and the space that ends it, which may make these
look strange to you, they are bit-selects like any other bit-select.

Is the I200_ port a bus?

Apparently, since it is being connected to vector that is created from
a concatenation of values.

In the SDF file I found the following line:
(INTERCONNECT linphy\/macro_1/I200_\[1\] i_pci_ad_pad30/TEN (0.001::0.001))

I don't know the SDF syntax, but based on this I assume that it uses a
different escaping syntax, with a backslash escaping each special character.
If so, then this seems to be trying to reference a signal with the name
"I200_[1]".

Which seems to be incorrect because Modelsim says:
# WARNING: ../test.sdf(6004): Failed to find port 'linphy/macro_1/I200_[1]'

Which seems to confirm my suspicions.

Presumably what was needed was a bit-select of the signal named "I200_"
instead. I would guess that one of your tools (the one producing the
Verilog code or the one producing the SDF) is getting confused between
bit-selects of vectors and escaped names containing bracketed numbers.
But since I don't know SDF syntax, I can't be sure.

 

[Rain Adelbert]

David Jones wrote:

In Verilog, a name that begins with a backslash is an "extended identifier",
which may contain any characters other than whitespace.

So, "\linphy/I200X " is an identifier. Note the space at the end -
this is required, otherwise the following comma would also be considered
part of the identifier.

Extended identifiers often arise during synthesis when the tool either
flattens hierarchy (which seems to have happened in your case) or smashes
buses (leading to names such as "\foo[2] ").

In your specific case, the [1], [2] etc. are standard indexing functions.


Yes, that was obvious, but first time it looked a bit strange to me

because I'm used to syntax where there is no space between index and
signal name.

In the SDF file I found the following line:
(INTERCONNECT linphy\/macro_1/I200_\[1\] i_pci_ad_pad30/TEN (0.001::0.001))

Which seems to be incorrect because Modelsim says:
# WARNING: ../test.sdf(6004): Failed to find port 'linphy/macro_1/I200_[1]'


You will need to look for a port with that name, or a name close to it.
You likely won't find it exactly, but the difference will tell you what
went wrong.

Yep, I replaced \[ and \] with [ and ] in SDF file and that solved my
problem. I got it quit soon after writing the mail. Sometimes it's
helpful to just write the problem down.

Thank you anyway!
Rain