Port bus order

[Kenneth Brun Nielsen]

I have a Verilog netlist exported from a Cadence environment where I
see strange behaviour.

Debugging it, it turns out that the order of a bus (vector?) port has
been declared as "big endian".

However I am surprised that the order actually makes a difference in
this case, since the port bits are connected one-by-one when the
module is instantiated.

Would you Verilog experts expect different behaviours from module A
and module B below?

module A (out[1], out[0], dummy, in[1], in[0] )
input dummy;
input [0:1] in;
output [0:1] out;
endmodule

module B (out[1], out[0], dummy, in[1], in[0] )
input dummy;
input [1:0] in;
output [1:0] out;
endmodule

Both modules are instantiated similar to the following:

module main (....)
.....

A/B (test[1], test[0], signal, generated[1], generated[0]);
....
endmodule

So in that context would you expect different behaviour between module
A and B?

BTW, I'm simulating in Icarus.

Best regards,
Kenneth

 

[glen herrmannsfeldt]

Kenneth Brun Nielsen <kenneth.brun.nielsen@googlemail.com> wrote:
< I have a Verilog netlist exported from a Cadence environment where I
< see strange behaviour.

< Debugging it, it turns out that the order of a bus (vector?)
< port has been declared as "big endian".

< However I am surprised that the order actually makes a difference in
< this case, since the port bits are connected one-by-one when the
< module is instantiated.

It depends on what you do with them, but in many cases it
doesn't matter.

< Would you Verilog experts expect different behaviours
< from module A and module B below?

< module A (out[1], out[0], dummy, in[1], in[0] )
< input dummy;
< input [0:1] in;
< output [0:1] out;
< endmodule

< module B (out[1], out[0], dummy, in[1], in[0] )
< input dummy;
< input [1:0] in;
< output [1:0] out;
< endmodule

I forgot you could even put port selectors on the module line.
Note, though, that the modules don't do anything. If it
has, for instance:

assign out={in[1],in[0]};

then the result would be different. As long as you only
reference without part selectors, or only reference with
part selectors, the result should be the same.

-- glen

 

[Kenneth Brun Nielsen]

On 6 Okt., 19:16, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Kenneth Brun Nielsen <kenneth.brun.niel...@googlemail.com> wrote:

module A (out[1], out[0], dummy, in[1], in[0] )
input dummy;
input [0:1] in;
output [0:1] out;
endmodule

module B (out[1], out[0], dummy, in[1], in[0] )
input dummy;
input [1:0] in;
output [1:0] out;
endmodule

I forgot you could even put port selectors on the module line.
Note, though, that the modules don't do anything.  If it
has, for instance:

    assign out={in[1],in[0]};

then the result would be different.  As long as you only
reference without part selectors, or only reference with
part selectors, the result should be the same.

Hi Glen,

OK. I did not not include the actual content of the module.

Here it is:

module example ( Out[6], Out[5], Out[4], Out[3], Out[2], Out[1], Out
[0], gnd, vdd, In[6], In[5], In[4], In[3], In[2], In[1], In[0] );
inout gnd, vdd;
output [6:0] Out;
input [6:0] In;
// opposed to: output [0:6] Out;
// opposed to: input [0:6] In;

SUBCELL1 I7 ( Out[0], In[0]);
SUBCELL2 I6 ( net21, Out[6], In[6], net20);
SUBCELL2 I5 ( net20, Out[5], In[5], net24);
SUBCELL2 I4 ( net24, Out[4], In[4], net28);
SUBCELL2 I3 ( net28, Out[3], In[3], net32);
SUBCELL2 I2 ( net32, Out[2], In[2], net36);
SUBCELL2 I1 ( net36, Out[1], In[1], In[0]);

endmodule

So, at this level in the hierarchy at least, the notations with and
without part selections are not mixed. And still, I experience the
difference.

Anyway, I managed to get rid of the part selections in the module
declarations by tweaking the export step. So I solved the problem in
another way now. However, I'm still surprised it makes a difference.

Best regards,
Kenneth

 

[glen herrmannsfeldt]

Kenneth Brun Nielsen <kenneth.brun.nielsen@googlemail.com> wrote:
< On 6 Okt., 19:16, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
<> Kenneth Brun Nielsen <kenneth.brun.niel...@googlemail.com> wrote:

(snip)
<> I forgot you could even put port selectors on the module line.
<> Note, though, that the modules don't do anything. ?If it
<> has, for instance:

<> ? ? assign out={in[1],in[0]};

<> then the result would be different. ?As long as you only
<> reference without part selectors, or only reference with
<> part selectors, the result should be the same.

< OK. I did not not include the actual content of the module.

< Here it is:

< module example ( Out[6], Out[5], Out[4], Out[3], Out[2], Out[1], Out
< [0], gnd, vdd, In[6], In[5], In[4], In[3], In[2], In[1], In[0] );
< inout gnd, vdd;
< output [6:0] Out;
< input [6:0] In;
< // opposed to: output [0:6] Out;
< // opposed to: input [0:6] In;

< SUBCELL1 I7 ( Out[0], In[0]);
< SUBCELL2 I6 ( net21, Out[6], In[6], net20);
< SUBCELL2 I5 ( net20, Out[5], In[5], net24);
< SUBCELL2 I4 ( net24, Out[4], In[4], net28);
< SUBCELL2 I3 ( net28, Out[3], In[3], net32);
< SUBCELL2 I2 ( net32, Out[2], In[2], net36);
< SUBCELL2 I1 ( net36, Out[1], In[1], In[0]);

< endmodule

< So, at this level in the hierarchy at least, the notations with and
< without part selections are not mixed. And still, I experience the
< difference.

Yes, it does look like that should be the same.

Note, though, that your debugging tools will likely display
the results in a different order in the two cases.

< Anyway, I managed to get rid of the part selections in the module
< declarations by tweaking the export step. So I solved the problem in
< another way now. However, I'm still surprised it makes a difference.

-- glen